exynos5420: Revamp the high speed I2C driver.
The previous driver was a bit awkward and not entirely correct. This change primarily replaces the read/write functions with simpler and more robust (hopefully) version. Change-Id: I55f0ad8faec2de520e27577bd6dad9c0118d8171 Signed-off-by: Gabe Black <gabeblack@chromium.org> Reviewed-on: http://review.coreboot.org/3684 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
This commit is contained in:
Gabe Black
Stefan Reinauer
parent
3511b92d31
commit
becb3f62f7
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@ -46,6 +46,14 @@
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#define HSI2C_TXCHON (1u << 7) /* Read/Receive */
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#define HSI2C_SW_RST (1u << 31)
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/* I2C_FIFO_STAT Register bits */
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#define HSI2C_TX_FIFO_LEVEL (0x7f << 0)
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#define HSI2C_TX_FIFO_FULL (1u << 7)
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#define HSI2C_TX_FIFO_EMPTY (1u << 8)
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#define HSI2C_RX_FIFO_LEVEL (0x7f << 16)
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#define HSI2C_RX_FIFO_FULL (1u << 23)
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#define HSI2C_RX_FIFO_EMPTY (1u << 24)
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/* I2C_FIFO_CTL Register bits */
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#define HSI2C_RXFIFO_EN (1u << 0)
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#define HSI2C_TXFIFO_EN (1u << 1)
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@ -77,11 +85,11 @@
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/* I2C_TRANS_STATUS register bits */
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#define HSI2C_MASTER_BUSY (1u << 17)
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#define HSI2C_SLAVE_BUSY (1u << 16)
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#define HSI2C_TIMEOUT_AUTO (1u << 4)
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#define HSI2C_NO_DEV (1u << 3)
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#define HSI2C_NO_DEV_ACK (1u << 2)
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#define HSI2C_TRANS_ABORT (1u << 1)
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#define HSI2C_TRANS_DONE (1u << 0)
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#define HSI2C_TIMEOUT_AUTO (0u << 0)
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#define HSI2C_SLV_ADDR_MAS(x) ((x & 0x3ff) << 10)
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@ -205,48 +213,11 @@ static int WaitForXfer(struct s3c24x0_i2c *i2c)
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return I2C_NOK_TOUT;
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}
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static int hsi2c_wait_for_irq(struct exynos5_hsi2c *i2c)
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{
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struct mono_time current, end;
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int ret = I2C_NOK_TOUT;
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timer_monotonic_get(¤t);
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end = current;
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mono_time_add_usecs(&end, HSI2C_TIMEOUT * 1000 * 10);
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while (mono_time_before(¤t, &end)) {
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udelay(20);
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if (read32(&i2c->usi_int_stat) &
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(HSI2C_INT_I2C_EN | HSI2C_INT_TX_ALMOSTEMPTY_EN)) {
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ret = I2C_OK;
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break;
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}
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/* wait for a while and retry */
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timer_monotonic_get(¤t);
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}
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if (ret == I2C_NOK_TOUT)
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printk(BIOS_ERR, "%s timed out\n", __func__);
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return ret;
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}
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static int hsi2c_isack(struct exynos5_hsi2c *i2c)
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{
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return read32(&i2c->usi_trans_status) &
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(HSI2C_NO_DEV | HSI2C_NO_DEV_ACK);
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}
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static void ReadWriteByte(struct s3c24x0_i2c *i2c)
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{
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writel(read32(&i2c->iiccon) & ~I2CCON_IRPND, &i2c->iiccon);
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}
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static void hsi2c_clear_irqpd(struct exynos5_hsi2c *i2c)
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{
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u32 stat = read32(&i2c->usi_int_stat);
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write32(stat, &i2c->usi_int_stat);
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}
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static void i2c_ch_init(struct s3c24x0_i2c_bus *bus, int speed, int slaveadd)
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{
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unsigned long freq, pres = 16, div;
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@ -346,6 +317,12 @@ static void hsi2c_ch_init(struct s3c24x0_i2c_bus *i2c_bus)
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write32(i2c_timing_s2, &hsregs->usi_timing_fs2);
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write32(i2c_timing_s3, &hsregs->usi_timing_fs3);
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write32(i2c_timing_sla, &hsregs->usi_timing_sla);
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/* Enable TXFIFO and RXFIFO */
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write32(HSI2C_RXFIFO_EN | HSI2C_TXFIFO_EN, &hsregs->usi_fifo_ctl);
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/* i2c_conf configure */
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write32(readl(&hsregs->usi_conf) | HSI2C_AUTO_MODE, &hsregs->usi_conf);
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}
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/* SW reset for the high speed bus */
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@ -386,34 +363,61 @@ void i2c_init(unsigned bus_num, int speed, int slaveadd)
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}
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/*
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* Send a STOP event and wait for it to have completed
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*
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* @param mode If it is a master transmitter or receiver
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* @return I2C_OK if the line became idle before timeout I2C_NOK_TOUT otherwise
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* Check whether the transfer is complete.
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*/
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static int hsi2c_send_stop(struct exynos5_hsi2c *i2c, int result)
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static int hsi2c_check_transfer(struct exynos5_hsi2c *i2c)
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{
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uint32_t status = read32(&i2c->usi_trans_status);
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if (status & HSI2C_TRANS_ABORT)
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printk(BIOS_ERR, "%s: Transaction aborted.\n", __func__);
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if (status & HSI2C_NO_DEV_ACK)
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printk(BIOS_ERR, "%s: No ack from device.\n", __func__);
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if (status & HSI2C_NO_DEV)
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printk(BIOS_ERR, "%s: No response from device.\n", __func__);
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if (status & HSI2C_TIMEOUT_AUTO)
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printk(BIOS_ERR, "%s: Transaction time out.\n", __func__);
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return !!(status & HSI2C_MASTER_BUSY);
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}
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/*
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* Wait for the transfer to finish.
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*/
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static int hsi2c_wait_for_transfer(struct exynos5_hsi2c *i2c)
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{
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int ret = I2C_NOK_TOUT;
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struct mono_time current, end;
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timer_monotonic_get(¤t);
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end = current;
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mono_time_add_usecs(&end, HSI2C_TIMEOUT * 1000);
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while (mono_time_before(¤t, &end)) {
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if (!(read32(&i2c->usi_trans_status) & HSI2C_MASTER_BUSY)) {
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ret = I2C_OK;
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break;
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}
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if (!hsi2c_check_transfer(i2c))
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return 0;
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udelay(5);
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timer_monotonic_get(¤t);
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}
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if (ret)
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printk(BIOS_ERR, "%s timed out\n", __func__);
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/* Setting the STOP event to fire */
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write32(HSI2C_FUNC_MODE_I2C, &i2c->usi_ctl);
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write32(0x0, &i2c->usi_int_en);
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return 1;
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}
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return (result == I2C_OK) ? ret : result;
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static int hsi2c_senddata(struct exynos5_hsi2c *i2c, uint8_t *data, int len)
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{
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while (hsi2c_check_transfer(i2c) && len) {
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if (!(read32(&i2c->usi_fifo_stat) & HSI2C_TX_FIFO_FULL)) {
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write32(*data++, &i2c->usi_txdata);
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len--;
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}
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}
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return len ? -1 : 0;
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}
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static int hsi2c_recvdata(struct exynos5_hsi2c *i2c, uint8_t *data, int len)
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{
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while (hsi2c_check_transfer(i2c) && len) {
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if (!(read32(&i2c->usi_fifo_stat) & HSI2C_RX_FIFO_EMPTY)) {
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*data++ = read32(&i2c->usi_rxdata);
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len--;
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}
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}
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return len ? -1 : 0;
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}
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static int hsi2c_write(struct exynos5_hsi2c *i2c,
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@ -423,83 +427,33 @@ static int hsi2c_write(struct exynos5_hsi2c *i2c,
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unsigned char data[],
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unsigned short len)
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{
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int i = 0, result = I2C_OK;
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u32 i2c_auto_conf;
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u32 stat;
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struct mono_time current, end;
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uint32_t i2c_auto_conf;
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/* Check I2C bus idle */
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i = HSI2C_TIMEOUT * 20;
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timer_monotonic_get(¤t);
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end = current;
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mono_time_add_usecs(&end, HSI2C_TIMEOUT * 1000 * 20);
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while (mono_time_before(¤t, &end)) {
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if (!(read32(&i2c->usi_trans_status) & HSI2C_MASTER_BUSY))
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break;
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udelay(50);
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timer_monotonic_get(¤t);
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}
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stat = read32(&i2c->usi_trans_status);
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if (stat & HSI2C_MASTER_BUSY) {
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printk(BIOS_ERR, "%s: bus busy, timing out\n", __func__);
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return I2C_NOK_TOUT;
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}
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/* Disable TXFIFO and RXFIFO */
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write32(0, &i2c->usi_fifo_ctl);
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if (hsi2c_wait_for_transfer(i2c))
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return -1;
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/* chip address */
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write32(HSI2C_SLV_ADDR_MAS(chip), &i2c->i2c_addr);
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/* Enable interrupts */
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write32((HSI2C_INT_I2C_EN | HSI2C_INT_TX_ALMOSTEMPTY_EN),
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&i2c->usi_int_en);
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/* usi_ctl enable i2c func, master write configure */
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write32((HSI2C_TXCHON | HSI2C_FUNC_MODE_I2C | HSI2C_MASTER),
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&i2c->usi_ctl);
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/* i2c_conf configure */
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write32(readl(&i2c->usi_conf) | HSI2C_AUTO_MODE, &i2c->usi_conf);
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/* auto_conf for write length and stop configure */
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i2c_auto_conf = ((len + alen) | HSI2C_STOP_AFTER_TRANS);
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i2c_auto_conf &= ~HSI2C_READ_WRITE;
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/* Master run, start xfer */
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i2c_auto_conf |= HSI2C_MASTER_RUN;
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write32(i2c_auto_conf, &i2c->usi_auto_conf);
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/* Master run, start xfer */
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write32(read32(&i2c->usi_auto_conf) | HSI2C_MASTER_RUN,
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&i2c->usi_auto_conf);
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result = hsi2c_wait_for_irq(i2c);
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if ((result == I2C_OK) && hsi2c_isack(i2c)) {
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printk(BIOS_ERR, "%s: NAK from device %04x\n", __func__,
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HSI2C_SLV_ADDR_MAS(chip));
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result = I2C_NACK;
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goto out;
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if (hsi2c_senddata(i2c, addr, alen) ||
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hsi2c_senddata(i2c, data, len) ||
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hsi2c_wait_for_transfer(i2c)) {
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return -1;
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}
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for (i = 0; i < alen && (result == I2C_OK); i++) {
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write32(addr[i], &i2c->usi_txdata);
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result = hsi2c_wait_for_irq(i2c);
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hsi2c_clear_irqpd(i2c);
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if (result)
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printk(BIOS_ERR, "%s: timeout on sending address\n",
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__func__);
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}
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for (i = 0; i < len && (result == I2C_OK); i++) {
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write32(data[i], &i2c->usi_txdata);
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result = hsi2c_wait_for_irq(i2c);
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hsi2c_clear_irqpd(i2c);
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if (result)
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printk(BIOS_ERR, "%s: timeout on sending data\n",
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__func__);
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}
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out:
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hsi2c_clear_irqpd(i2c);
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return hsi2c_send_stop(i2c, result);
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write32(HSI2C_FUNC_MODE_I2C, &i2c->usi_ctl);
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return 0;
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}
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static int hsi2c_read(struct exynos5_hsi2c *i2c,
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@ -510,60 +464,45 @@ static int hsi2c_read(struct exynos5_hsi2c *i2c,
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unsigned short len,
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int check)
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{
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int i, result;
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u32 i2c_auto_conf;
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if (!check) {
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result = hsi2c_write(i2c, chip, addr, alen, data, 0);
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if (result != I2C_OK) {
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printk(BIOS_ERR, "write failed Result: %d\n", result);
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return result;
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}
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}
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uint32_t i2c_auto_conf;
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/* start read */
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/* Disable TXFIFO and RXFIFO */
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write32(0, &i2c->usi_fifo_ctl);
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if (hsi2c_wait_for_transfer(i2c))
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return -1;
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/* chip address */
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write32(HSI2C_SLV_ADDR_MAS(chip), &i2c->i2c_addr);
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/* Enable interrupts */
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write32(HSI2C_INT_I2C_EN, &i2c->usi_int_en);
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/* usi_ctl enable i2c func, master write configure */
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write32((HSI2C_TXCHON | HSI2C_FUNC_MODE_I2C | HSI2C_MASTER),
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&i2c->usi_ctl);
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/* i2c_conf configure */
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write32(read32(&i2c->usi_conf) | HSI2C_AUTO_MODE, &i2c->usi_conf);
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/* auto_conf */
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write32(alen | HSI2C_MASTER_RUN | HSI2C_STOP_AFTER_TRANS,
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&i2c->usi_auto_conf);
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/* auto_conf, length and stop configure */
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i2c_auto_conf = (len | HSI2C_STOP_AFTER_TRANS | HSI2C_READ_WRITE);
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write32(i2c_auto_conf, &i2c->usi_auto_conf);
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if (hsi2c_senddata(i2c, addr, alen) ||
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hsi2c_wait_for_transfer(i2c)) {
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return -1;
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}
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/* usi_ctl enable i2c func, master WRITE configure */
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write32((HSI2C_RXCHON | HSI2C_FUNC_MODE_I2C | HSI2C_MASTER),
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&i2c->usi_ctl);
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/* auto_conf, length and stop configure */
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i2c_auto_conf = (len | HSI2C_STOP_AFTER_TRANS | HSI2C_READ_WRITE);
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i2c_auto_conf |= HSI2C_MASTER_RUN;
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/* Master run, start xfer */
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write32(readl(&i2c->usi_auto_conf) | HSI2C_MASTER_RUN,
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&i2c->usi_auto_conf);
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write32(i2c_auto_conf, &i2c->usi_auto_conf);
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result = hsi2c_wait_for_irq(i2c);
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if ((result == I2C_OK) && hsi2c_isack(i2c)) {
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result = I2C_NACK;
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goto out;
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if (hsi2c_recvdata(i2c, data, len) ||
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hsi2c_wait_for_transfer(i2c)) {
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return -1;
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}
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for (i = 0; i < len && (result == I2C_OK); i++) {
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result = hsi2c_wait_for_irq(i2c);
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data[i] = read32(&i2c->usi_rxdata);
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udelay(100);
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}
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/*for(i = 0; i < len; i++)
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printk(BIOS_SPEW, " %02x", data[i]);
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printk(BIOS_SPEW, "\n");*/
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out:
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/* Stop and quit */
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hsi2c_clear_irqpd(i2c);
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return hsi2c_send_stop(i2c, result);
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write32(HSI2C_FUNC_MODE_I2C, &i2c->usi_ctl);
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return 0;
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}
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/*
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