sb,nb/intel/fsp_rangeley: Rename from xx_DEV_FUNC
Intel adopted xx_DEVFN_xx naming for macros expanding to PCI_DEVFN() starting with apollolake. The ones named xx_DEV_FUNC are being renamed, or dropped, if they were generally not used at all for a platform. Change-Id: I6ead2bc5e41a86c9aeef730f5664a30406414c8c Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35730 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
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@ -52,7 +52,7 @@ static void ConfigureDefaultUpdData(UPD_DATA_REGION *UpdData)
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DEVTREE_CONST config_t *config;
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printk(BIOS_DEBUG, "Configure Default UPD Data\n");
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dev = pcidev_path_on_root(SOC_DEV_FUNC);
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dev = pcidev_path_on_root(SOC_DEVFN_SOC);
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config = dev->chip_info;
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/* Set SPD addresses */
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@ -103,30 +103,30 @@ static void ConfigureDefaultUpdData(UPD_DATA_REGION *UpdData)
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continue;
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switch (dev->path.pci.devfn) {
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case GBE1_DEV_FUNC:
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case GBE2_DEV_FUNC:
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case GBE3_DEV_FUNC:
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case GBE4_DEV_FUNC:
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case SOC_DEVFN_GBE1:
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case SOC_DEVFN_GBE2:
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case SOC_DEVFN_GBE3:
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case SOC_DEVFN_GBE4:
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UpdData->PcdEnableLan |= dev->enabled;
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printk(BIOS_DEBUG, "PcdEnableLan %d\n",
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UpdData->PcdEnableLan);
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break;
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case SATA2_DEV_FUNC:
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case SOC_DEVFN_SATA2:
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UpdData->PcdEnableSata2 = dev->enabled;
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printk(BIOS_DEBUG, "PcdEnableSata2 %d\n",
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UpdData->PcdEnableSata2);
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break;
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case SATA3_DEV_FUNC:
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case SOC_DEVFN_SATA3:
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UpdData->PcdEnableSata3 = dev->enabled;
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printk(BIOS_DEBUG, "PcdEnableSata3 %d\n",
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UpdData->PcdEnableSata3);
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break;
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case IQAT_DEV_FUNC:
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case SOC_DEVFN_IQAT:
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UpdData->PcdEnableIQAT |= dev->enabled;
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printk(BIOS_DEBUG, "PcdEnableIQAT %d\n",
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UpdData->PcdEnableIQAT);
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break;
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case USB2_DEV_FUNC:
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case SOC_DEVFN_USB2:
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UpdData->PcdEnableUsb20 = dev->enabled;
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printk(BIOS_DEBUG, "PcdEnableUsb20 %d\n",
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UpdData->PcdEnableUsb20);
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@ -26,72 +26,72 @@
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/* Host Bridge */
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#define SOC_DEV 0x0
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#define SOC_FUNC 0
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# define SOC_DEV_FUNC PCI_DEVFN(SOC_DEV,SOC_FUNC)
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# define SOC_DEVFN_SOC PCI_DEVFN(SOC_DEV,SOC_FUNC)
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/* PCIE Port 1 */
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#define PCIE_PORT1_DEV 0x1
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#define PCIE_PORT1_FUNC 0
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# define PCIE_PORT1_DEV_FUNC PCI_DEVFN(PCIE_PORT1_DEV,PCIE_PORT1_FUNC)
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# define SOC_DEVFN_PCIE_PORT1 PCI_DEVFN(PCIE_PORT1_DEV,PCIE_PORT1_FUNC)
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/* PCIE Port 2 */
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#define PCIE_PORT2_DEV 0x2
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#define PCIE_PORT2_FUNC 0
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# define PCIE_PORT2_DEV_FUNC PCI_DEVFN(PCIE_PORT2_DEV,PCIE_PORT2_FUNC)
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# define SOC_DEVFN_PCIE_PORT2 PCI_DEVFN(PCIE_PORT2_DEV,PCIE_PORT2_FUNC)
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/* PCIE Port 3 */
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#define PCIE_PORT3_DEV 0x3
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#define PCIE_PORT3_FUNC 0
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# define PCIE_PORT3_DEV_FUNC PCI_DEVFN(PCIE_PORT3_DEV,PCIE_PORT3_FUNC)
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# define SOC_DEVFN_PCIE_PORT3 PCI_DEVFN(PCIE_PORT3_DEV,PCIE_PORT3_FUNC)
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/* PCIE Port 4 */
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#define PCIE_PORT4_DEV 0x4
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#define PCIE_PORT4_FUNC 0
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# define PCIE_PORT4_DEV_FUNC PCI_DEVFN(PCIE_PORT4_DEV,PCIE_PORT4_FUNC)
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# define SOC_DEVFN_PCIE_PORT4 PCI_DEVFN(PCIE_PORT4_DEV,PCIE_PORT4_FUNC)
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/* Host Bridge, Fabric, and RAS Registers */
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#define HOST_BRIDGE_DEV 0xe
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#define HOST_BRIDGE_FUNC 0
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# define HOST_BRIDGE_DEV_FUNC PCI_DEVFN(HOST_BRIDGE_DEV,HOST_BRIDGE_FUNC)
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# define SOC_DEVFN_HOST_BRIDGE PCI_DEVFN(HOST_BRIDGE_DEV,HOST_BRIDGE_FUNC)
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/* Root Complex Event Collector (RCEC) */
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#define RCEC_DEV 0xf
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#define RCEC_FUNC 0
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# define RCEC_DEV_FUNC PCI_DEVFN(RCEC_DEV,RCEC_FUNC)
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# define SOC_DEVFN_RCEC PCI_DEVFN(RCEC_DEV,RCEC_FUNC)
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/* SMBus 2.0 1 */
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#define SMBUS1_DEV 0x13
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#define SMBUS1_FUNC 0
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# define SMBUS1_DEV_FUNC PCI_DEVFN(SMBUS1_DEV,SMBUS1_FUNC)
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# define SOC_DEVFN_SMBUS1 PCI_DEVFN(SMBUS1_DEV,SMBUS1_FUNC)
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/* Gigabit Ethernet (GbE) */
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#define GBE_DEV 0x14
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#define GBE1_DEV GBE_DEV
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#define GBE1_FUNC 0
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# define GBE1_DEV_FUNC PCI_DEVFN(GBE1_DEV,GBE1_FUNC)
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# define SOC_DEVFN_GBE1 PCI_DEVFN(GBE1_DEV,GBE1_FUNC)
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#define GBE2_DEV GBE_DEV
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#define GBE2_FUNC 1
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# define GBE2_DEV_FUNC PCI_DEVFN(GBE2_DEV,GBE2_FUNC)
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# define SOC_DEVFN_GBE2 PCI_DEVFN(GBE2_DEV,GBE2_FUNC)
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#define GBE3_DEV GBE_DEV
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#define GBE3_FUNC 2
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# define GBE3_DEV_FUNC PCI_DEVFN(GBE3_DEV,GBE3_FUNC)
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# define SOC_DEVFN_GBE3 PCI_DEVFN(GBE3_DEV,GBE3_FUNC)
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#define GBE4_DEV GBE_DEV
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#define GBE4_FUNC 3
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# define GBE4_DEV_FUNC PCI_DEVFN(GBE4_DEV,GBE4_FUNC)
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# define SOC_DEVFN_GBE4 PCI_DEVFN(GBE4_DEV,GBE4_FUNC)
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/* USB 2.0 */
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#define USB2_DEV 0x16
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#define USB2_FUNC 0
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# define USB2_DEV_FUNC PCI_DEVFN(USB2_DEV,USB2_FUNC)
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# define SOC_DEVFN_USB2 PCI_DEVFN(USB2_DEV,USB2_FUNC)
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/* SATA Gen 2 */
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#define SATA2_DEV 0x17
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#define SATA2_FUNC 0
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# define SATA2_DEV_FUNC PCI_DEVFN(SATA2_DEV,SATA2_FUNC)
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# define SOC_DEVFN_SATA2 PCI_DEVFN(SATA2_DEV,SATA2_FUNC)
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/* SATA Gen 3 */
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#define SATA3_DEV 0x18
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#define SATA3_FUNC 0
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# define SATA3_DEV_FUNC PCI_DEVFN(SATA3_DEV,SATA3_FUNC)
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# define SOC_DEVFN_SATA3 PCI_DEVFN(SATA3_DEV,SATA3_FUNC)
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/* Platform Control Unit (PCU) */
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#define PCU_DEV 0x1f
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@ -99,18 +99,18 @@
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/* Low Pin Count (LPC/ISA) */
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#define LPC_DEV PCU_DEV
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#define LPC_FUNC 0
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# define LPC_DEV_FUNC PCI_DEVFN(LPC_DEV,LPC_FUNC)
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# define SOC_DEVFN_LPC PCI_DEVFN(LPC_DEV,LPC_FUNC)
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# define LPC_BDF PCI_DEV(BUS0, LPC_DEV, LPC_FUNC)
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/* SMBus 2.0 0 */
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#define SMBUS0_DEV PCU_DEV
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#define SMBUS0_FUNC 3
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# define SMBUS0_DEV_FUNC PCI_DEVFN(SMBUS0_DEV,SMBUS0_FUNC)
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# define SOC_DEVFN_SMBUS0 PCI_DEVFN(SMBUS0_DEV,SMBUS0_FUNC)
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/* Intel QuickAssist Integrated Accelerator (IQIA) */
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#define IQAT_DEV 0xb
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#define IQAT_FUNC 0
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# define IQAT_DEV_FUNC PCI_DEVFN(IQAT_DEV,IQAT_FUNC)
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# define SOC_DEVFN_IQAT PCI_DEVFN(IQAT_DEV,IQAT_FUNC)
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#define SOC_DEVID 0x1f08
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#define PCIE_PORT1_DEVID 0x1f10
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