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sb,nb/intel/fsp_rangeley: Rename from xx_DEV_FUNC 

Intel adopted xx_DEVFN_xx naming for macros expanding to
PCI_DEVFN() starting with apollolake. The ones named
xx_DEV_FUNC are being renamed, or dropped, if they
were generally not used at all for a platform.

Change-Id: I6ead2bc5e41a86c9aeef730f5664a30406414c8c
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35730
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
This commit is contained in:
Kyösti Mälkki 2019-09-30 13:02:34 +03:00
parent 17e9bcb9b8
commit beceea29d1
2 changed files with 27 additions and 27 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

18
src/northbridge/intel/fsp_rangeley/fsp/chipset_fsp_util.c
View File

@ -52,7 +52,7 @@ static void ConfigureDefaultUpdData(UPD_DATA_REGION *UpdData)
DEVTREE_CONST config_t *config; DEVTREE_CONST config_t *config;
printk(BIOS_DEBUG, "Configure Default UPD Data\n"); printk(BIOS_DEBUG, "Configure Default UPD Data\n");
dev = pcidev_path_on_root(SOC_DEV_FUNC); dev = pcidev_path_on_root(SOC_DEVFN_SOC);
config = dev->chip_info; config = dev->chip_info;
/* Set SPD addresses */ /* Set SPD addresses */
@ -103,30 +103,30 @@ static void ConfigureDefaultUpdData(UPD_DATA_REGION *UpdData)
continue; continue;
switch (dev->path.pci.devfn) { switch (dev->path.pci.devfn) {
case GBE1_DEV_FUNC: case SOC_DEVFN_GBE1:
case GBE2_DEV_FUNC: case SOC_DEVFN_GBE2:
case GBE3_DEV_FUNC: case SOC_DEVFN_GBE3:
case GBE4_DEV_FUNC: case SOC_DEVFN_GBE4:
UpdData->PcdEnableLan |= dev->enabled; UpdData->PcdEnableLan |= dev->enabled;
printk(BIOS_DEBUG, "PcdEnableLan %d\n", printk(BIOS_DEBUG, "PcdEnableLan %d\n",
UpdData->PcdEnableLan); UpdData->PcdEnableLan);
break; break;
case SATA2_DEV_FUNC: case SOC_DEVFN_SATA2:
UpdData->PcdEnableSata2 = dev->enabled; UpdData->PcdEnableSata2 = dev->enabled;
printk(BIOS_DEBUG, "PcdEnableSata2 %d\n", printk(BIOS_DEBUG, "PcdEnableSata2 %d\n",
UpdData->PcdEnableSata2); UpdData->PcdEnableSata2);
break; break;
case SATA3_DEV_FUNC: case SOC_DEVFN_SATA3:
UpdData->PcdEnableSata3 = dev->enabled; UpdData->PcdEnableSata3 = dev->enabled;
printk(BIOS_DEBUG, "PcdEnableSata3 %d\n", printk(BIOS_DEBUG, "PcdEnableSata3 %d\n",
UpdData->PcdEnableSata3); UpdData->PcdEnableSata3);
break; break;
case IQAT_DEV_FUNC: case SOC_DEVFN_IQAT:
UpdData->PcdEnableIQAT |= dev->enabled; UpdData->PcdEnableIQAT |= dev->enabled;
printk(BIOS_DEBUG, "PcdEnableIQAT %d\n", printk(BIOS_DEBUG, "PcdEnableIQAT %d\n",
UpdData->PcdEnableIQAT); UpdData->PcdEnableIQAT);
break; break;
case USB2_DEV_FUNC: case SOC_DEVFN_USB2:
UpdData->PcdEnableUsb20 = dev->enabled; UpdData->PcdEnableUsb20 = dev->enabled;
printk(BIOS_DEBUG, "PcdEnableUsb20 %d\n", printk(BIOS_DEBUG, "PcdEnableUsb20 %d\n",
UpdData->PcdEnableUsb20); UpdData->PcdEnableUsb20);

36
src/southbridge/intel/fsp_rangeley/pci_devs.h
View File

@ -26,72 +26,72 @@
/* Host Bridge */ /* Host Bridge */
#define SOC_DEV 0x0 #define SOC_DEV 0x0
#define SOC_FUNC 0 #define SOC_FUNC 0
# define SOC_DEV_FUNC PCI_DEVFN(SOC_DEV,SOC_FUNC) # define SOC_DEVFN_SOC PCI_DEVFN(SOC_DEV,SOC_FUNC)
/* PCIE Port 1 */ /* PCIE Port 1 */
#define PCIE_PORT1_DEV 0x1 #define PCIE_PORT1_DEV 0x1
#define PCIE_PORT1_FUNC 0 #define PCIE_PORT1_FUNC 0
# define PCIE_PORT1_DEV_FUNC PCI_DEVFN(PCIE_PORT1_DEV,PCIE_PORT1_FUNC) # define SOC_DEVFN_PCIE_PORT1 PCI_DEVFN(PCIE_PORT1_DEV,PCIE_PORT1_FUNC)
/* PCIE Port 2 */ /* PCIE Port 2 */
#define PCIE_PORT2_DEV 0x2 #define PCIE_PORT2_DEV 0x2
#define PCIE_PORT2_FUNC 0 #define PCIE_PORT2_FUNC 0
# define PCIE_PORT2_DEV_FUNC PCI_DEVFN(PCIE_PORT2_DEV,PCIE_PORT2_FUNC) # define SOC_DEVFN_PCIE_PORT2 PCI_DEVFN(PCIE_PORT2_DEV,PCIE_PORT2_FUNC)
/* PCIE Port 3 */ /* PCIE Port 3 */
#define PCIE_PORT3_DEV 0x3 #define PCIE_PORT3_DEV 0x3
#define PCIE_PORT3_FUNC 0 #define PCIE_PORT3_FUNC 0
# define PCIE_PORT3_DEV_FUNC PCI_DEVFN(PCIE_PORT3_DEV,PCIE_PORT3_FUNC) # define SOC_DEVFN_PCIE_PORT3 PCI_DEVFN(PCIE_PORT3_DEV,PCIE_PORT3_FUNC)
/* PCIE Port 4 */ /* PCIE Port 4 */
#define PCIE_PORT4_DEV 0x4 #define PCIE_PORT4_DEV 0x4
#define PCIE_PORT4_FUNC 0 #define PCIE_PORT4_FUNC 0
# define PCIE_PORT4_DEV_FUNC PCI_DEVFN(PCIE_PORT4_DEV,PCIE_PORT4_FUNC) # define SOC_DEVFN_PCIE_PORT4 PCI_DEVFN(PCIE_PORT4_DEV,PCIE_PORT4_FUNC)
/* Host Bridge, Fabric, and RAS Registers */ /* Host Bridge, Fabric, and RAS Registers */
#define HOST_BRIDGE_DEV 0xe #define HOST_BRIDGE_DEV 0xe
#define HOST_BRIDGE_FUNC 0 #define HOST_BRIDGE_FUNC 0
# define HOST_BRIDGE_DEV_FUNC PCI_DEVFN(HOST_BRIDGE_DEV,HOST_BRIDGE_FUNC) # define SOC_DEVFN_HOST_BRIDGE PCI_DEVFN(HOST_BRIDGE_DEV,HOST_BRIDGE_FUNC)
/* Root Complex Event Collector (RCEC) */ /* Root Complex Event Collector (RCEC) */
#define RCEC_DEV 0xf #define RCEC_DEV 0xf
#define RCEC_FUNC 0 #define RCEC_FUNC 0
# define RCEC_DEV_FUNC PCI_DEVFN(RCEC_DEV,RCEC_FUNC) # define SOC_DEVFN_RCEC PCI_DEVFN(RCEC_DEV,RCEC_FUNC)
/* SMBus 2.0 1 */ /* SMBus 2.0 1 */
#define SMBUS1_DEV 0x13 #define SMBUS1_DEV 0x13
#define SMBUS1_FUNC 0 #define SMBUS1_FUNC 0
# define SMBUS1_DEV_FUNC PCI_DEVFN(SMBUS1_DEV,SMBUS1_FUNC) # define SOC_DEVFN_SMBUS1 PCI_DEVFN(SMBUS1_DEV,SMBUS1_FUNC)
/* Gigabit Ethernet (GbE) */ /* Gigabit Ethernet (GbE) */
#define GBE_DEV 0x14 #define GBE_DEV 0x14
#define GBE1_DEV GBE_DEV #define GBE1_DEV GBE_DEV
#define GBE1_FUNC 0 #define GBE1_FUNC 0
# define GBE1_DEV_FUNC PCI_DEVFN(GBE1_DEV,GBE1_FUNC) # define SOC_DEVFN_GBE1 PCI_DEVFN(GBE1_DEV,GBE1_FUNC)
#define GBE2_DEV GBE_DEV #define GBE2_DEV GBE_DEV
#define GBE2_FUNC 1 #define GBE2_FUNC 1
# define GBE2_DEV_FUNC PCI_DEVFN(GBE2_DEV,GBE2_FUNC) # define SOC_DEVFN_GBE2 PCI_DEVFN(GBE2_DEV,GBE2_FUNC)
#define GBE3_DEV GBE_DEV #define GBE3_DEV GBE_DEV
#define GBE3_FUNC 2 #define GBE3_FUNC 2
# define GBE3_DEV_FUNC PCI_DEVFN(GBE3_DEV,GBE3_FUNC) # define SOC_DEVFN_GBE3 PCI_DEVFN(GBE3_DEV,GBE3_FUNC)
#define GBE4_DEV GBE_DEV #define GBE4_DEV GBE_DEV
#define GBE4_FUNC 3 #define GBE4_FUNC 3
# define GBE4_DEV_FUNC PCI_DEVFN(GBE4_DEV,GBE4_FUNC) # define SOC_DEVFN_GBE4 PCI_DEVFN(GBE4_DEV,GBE4_FUNC)
/* USB 2.0 */ /* USB 2.0 */
#define USB2_DEV 0x16 #define USB2_DEV 0x16
#define USB2_FUNC 0 #define USB2_FUNC 0
# define USB2_DEV_FUNC PCI_DEVFN(USB2_DEV,USB2_FUNC) # define SOC_DEVFN_USB2 PCI_DEVFN(USB2_DEV,USB2_FUNC)
/* SATA Gen 2 */ /* SATA Gen 2 */
#define SATA2_DEV 0x17 #define SATA2_DEV 0x17
#define SATA2_FUNC 0 #define SATA2_FUNC 0
# define SATA2_DEV_FUNC PCI_DEVFN(SATA2_DEV,SATA2_FUNC) # define SOC_DEVFN_SATA2 PCI_DEVFN(SATA2_DEV,SATA2_FUNC)
/* SATA Gen 3 */ /* SATA Gen 3 */
#define SATA3_DEV 0x18 #define SATA3_DEV 0x18
#define SATA3_FUNC 0 #define SATA3_FUNC 0
# define SATA3_DEV_FUNC PCI_DEVFN(SATA3_DEV,SATA3_FUNC) # define SOC_DEVFN_SATA3 PCI_DEVFN(SATA3_DEV,SATA3_FUNC)
/* Platform Control Unit (PCU) */ /* Platform Control Unit (PCU) */
#define PCU_DEV 0x1f #define PCU_DEV 0x1f
@ -99,18 +99,18 @@
/* Low Pin Count (LPC/ISA) */ /* Low Pin Count (LPC/ISA) */
#define LPC_DEV PCU_DEV #define LPC_DEV PCU_DEV
#define LPC_FUNC 0 #define LPC_FUNC 0
# define LPC_DEV_FUNC PCI_DEVFN(LPC_DEV,LPC_FUNC) # define SOC_DEVFN_LPC PCI_DEVFN(LPC_DEV,LPC_FUNC)
# define LPC_BDF PCI_DEV(BUS0, LPC_DEV, LPC_FUNC) # define LPC_BDF PCI_DEV(BUS0, LPC_DEV, LPC_FUNC)
/* SMBus 2.0 0 */ /* SMBus 2.0 0 */
#define SMBUS0_DEV PCU_DEV #define SMBUS0_DEV PCU_DEV
#define SMBUS0_FUNC 3 #define SMBUS0_FUNC 3
# define SMBUS0_DEV_FUNC PCI_DEVFN(SMBUS0_DEV,SMBUS0_FUNC) # define SOC_DEVFN_SMBUS0 PCI_DEVFN(SMBUS0_DEV,SMBUS0_FUNC)
/* Intel QuickAssist Integrated Accelerator (IQIA) */ /* Intel QuickAssist Integrated Accelerator (IQIA) */
#define IQAT_DEV 0xb #define IQAT_DEV 0xb
#define IQAT_FUNC 0 #define IQAT_FUNC 0
# define IQAT_DEV_FUNC PCI_DEVFN(IQAT_DEV,IQAT_FUNC) # define SOC_DEVFN_IQAT PCI_DEVFN(IQAT_DEV,IQAT_FUNC)
#define SOC_DEVID 0x1f08 #define SOC_DEVID 0x1f08
#define PCIE_PORT1_DEVID 0x1f10 #define PCIE_PORT1_DEVID 0x1f10