diff --git a/src/soc/intel/common/block/cse/Kconfig b/src/soc/intel/common/block/cse/Kconfig
index 55a2b49194..2962a1472e 100644
--- a/src/soc/intel/common/block/cse/Kconfig
+++ b/src/soc/intel/common/block/cse/Kconfig
@@ -54,6 +54,19 @@ config SOC_INTEL_CSE_SEND_EOP_EARLY
 	  In later stages, CSE might be busy and might require more time to process EOP command.
 	  SoC can use this Kconfig to send EOP earlier by itself.
 
+config SOC_INTEL_CSE_SEND_EOP_LATE
+	bool
+	depends on SOC_INTEL_COMMON_BLOCK_CSE
+	help
+	  Use this config to send End Of Post (EOP) late (even after CSE `final` operation)
+	  using boot state either `BS_PAYLOAD_BOOT` or `BS_PAYLOAD_LOAD` from common code
+	  in order to reduce time required to send EOP and getting CSE response.
+	  It has been observed that CSE might be busy and might require more time to
+	  process the EOP command.
+	  SoC can use this Kconfig to send EOP later by itself.
+	  Starting with Jasper Lake, coreboot sends EOP before loading payload hence, this
+	  config is applicable for those platforms.
+
 config SOC_INTEL_CSE_LITE_SKU
 	bool
 	default n
diff --git a/src/soc/intel/jasperlake/Kconfig b/src/soc/intel/jasperlake/Kconfig
index e7b486be04..183657445d 100644
--- a/src/soc/intel/jasperlake/Kconfig
+++ b/src/soc/intel/jasperlake/Kconfig
@@ -60,6 +60,7 @@ config CPU_SPECIFIC_OPTIONS
 	select SOC_INTEL_COMMON_FSP_RESET
 	select SOC_INTEL_COMMON_PCH_CLIENT
 	select SOC_INTEL_COMMON_RESET
+	select SOC_INTEL_CSE_SEND_EOP_LATE
 	select SOC_INTEL_CSE_SET_EOP
 	select SOC_INTEL_MEM_MAPPED_PM_CONFIGURATION
 	select SSE2
diff --git a/src/soc/intel/tigerlake/Kconfig b/src/soc/intel/tigerlake/Kconfig
index 4d87192922..bcf4a82655 100644
--- a/src/soc/intel/tigerlake/Kconfig
+++ b/src/soc/intel/tigerlake/Kconfig
@@ -80,6 +80,7 @@ config CPU_SPECIFIC_OPTIONS
 	select SOC_INTEL_COMMON_PCH_CLIENT
 	select SOC_INTEL_COMMON_RESET
 	select SOC_INTEL_COMMON_BLOCK_POWER_LIMIT
+	select SOC_INTEL_CSE_SEND_EOP_LATE
 	select SOC_INTEL_CSE_SET_EOP
 	select SOC_INTEL_MEM_MAPPED_PM_CONFIGURATION
 	select SSE2