soc/intel/common/cse: Late sending EOP msg if !HECI_DISABLE_USING_SMM
Pushing EOP msg post FSP notify helps to save ~30ms+ boot time across various warm reboots. This patch ensures late sending EOP msg when function disabling of CSE is no longer a requirement. BUG=b:200644229 TEST=Able to save ~30ms+ of boot time Without this code change EOP sending timestamp as below: 943:after sending EOP to ME 1,248,328(61,954)) With this code change EOP sending timestamp as below: 943:after sending EOP to ME 1,231,660 (2,754) Change-Id: I2b78a1c07803aacfb34dce9e94b2a05a2491aabc Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57806 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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@ -185,10 +185,15 @@ static void set_cse_end_of_post(void *unused)
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/*
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* Ideally, to give coreboot maximum flexibility, sending EOP would be done as
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* late possible, just before loading the payload, which would be BS_ON_EXIT
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* here, but the platforms this is currently supported for all select
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* HECI_DISABLE_USING_SMM, which runs in BS_ON_EXIT. Because sending EOP
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* requires HECI to be up, and it is not trivial to control the order in which
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* these callbacks are issued, it is called on BS_ON_ENTRY.
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* late possible. If HECI_DISABLE_USING_SMM is selected, then sending EOP must
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* be performed before the HECI bus is disabled, so these boards use
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* BS_PAYLOAD_LOAD, which happens before the HECI_DISABLE_USING_SMM Kconfig takes
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* effect (EOP is sent using the HECI bus).
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* Otherwise, EOP can be pushed a little later, and can be performed in
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* BS_PAYLOAD_BOOT instead.
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*/
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#if !CONFIG(HECI_DISABLE_USING_SMM)
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BOOT_STATE_INIT_ENTRY(BS_PAYLOAD_BOOT, BS_ON_ENTRY, set_cse_end_of_post, NULL);
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#else
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BOOT_STATE_INIT_ENTRY(BS_PAYLOAD_LOAD, BS_ON_ENTRY, set_cse_end_of_post, NULL);
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#endif
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