GNUBoot
/
coreboot-kgpe-d16
2
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

soc/intel/tgl: Enable USB4 resources based on common Kconfig 

Intel TGL BIOS specification (doc ##611569) Revision 0.7.6 Section
7.2.5.1.5 recommends reserving the following resources for each PCIe
USB4 root port:

 - 42 buses
 - 194 MiB Non-prefetchable memory
 - 448 MiB Prefetchable memory

This change enables reserving of resources for USB4 when mainboard
selects the newly added Kconfig SOC_INTEL_ENABLE_USB4_PCIE_RESOURCES.

This is similar to the change for ADL in commit 8d11cdc6fa
("soc/intel/alderlake: Add Kconfig for recommended PCIe TBT resources").

Change-Id: I25ec3f74ebd5727fa4b13f5a3b11050f77ecb008
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57125
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
This commit is contained in:
Furquan Shaikh 2021-08-24 13:42:05 -07:00
parent 8edbba4cc4
commit bee831e958
1 changed files with 18 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

18
src/soc/intel/tigerlake/Kconfig
View File

@ -287,4 +287,22 @@ config SOC_INTEL_CRASHLOG
help help
Enables CrashLog. Enables CrashLog.
# Intel recommends reserving the following resources per USB4 root port,
# from TGL BIOS Spec (doc #611569) Revision 0.7.6 Section 7.2.5.1.5
# - 42 buses
# - 194 MiB Non-prefetchable memory
# - 448 MiB Prefetchable memory
if SOC_INTEL_ENABLE_USB4_PCIE_RESOURCES
config PCIEXP_HOTPLUG_BUSES
default 42
config PCIEXP_HOTPLUG_MEM
default 0xc200000 # 194 MiB
config PCIEXP_HOTPLUG_PREFETCH_MEM
default 0x1c000000 # 448 MiB
endif # SOC_INTEL_ENABLE_USB4_PCIE_RESOURCES
endif endif