GNUBoot
/
coreboot-kgpe-d16
2
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

mb/google/brya0: Enable MIPI UFC 

1. Add 2 port 2 endpoint
2. Add support for OVTI5675
3. Guard entries in override device tree by FW_CONFIG

MIPI UFC is on I2C2
This configuration is as per P2 schematics

BUG=b:190674542
TEST=Build and Boot on Brya

Signed-off-by: Varshit B Pandya <varshit.b.pandya@intel.com>
Change-Id: Id3ef974994fd0d447e398b365cdf01d78c94cc4c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55670
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
This commit is contained in:
Varshit B Pandya 2021-06-18 20:18:50 +05:30 committed by Tim Wawrzynczak
parent 53435eac51
commit bee9d6028e
1 changed files with 66 additions and 2 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

68
src/mainboard/google/brya/variants/brya0/overridetree.cb
View File

@ -126,7 +126,26 @@ chip soc/intel/alderlake
register "cio2_lanes_used" = "{4}" # 4 CSI Camera lanes are used
register "cio2_lane_endpoint[0]" = ""^I2C0.CAM0""
register "cio2_prt[0]" = "2"
device generic 0 on end
device generic 0 on
# MIPI lanes are split between UFC and WFC depending on
# whether the UFC is USB or MIPI hence probing UFC_USB
probe UFC UFC_USB
end
end
chip drivers/intel/mipi_camera
register "acpi_uid" = "0x50000"
register "acpi_name" = ""IPU0""
register "device_type" = "INTEL_ACPI_CAMERA_CIO2"
register "cio2_num_ports" = "2"
register "cio2_lanes_used" = "{4,2}" # 4 and 2 CSI Camera lanes are used
register "cio2_lane_endpoint[0]" = ""^I2C0.CAM0""
register "cio2_lane_endpoint[1]" = ""^I2C2.CAM1""
register "cio2_prt[0]" = "2"
register "cio2_prt[1]" = "1"
device generic 0 on
probe UFC UFC_MIPI_5675
end
end
end
device ref cnvi_wifi on
@ -401,6 +420,49 @@ chip soc/intel/alderlake
register "reg_adv_ctrl20" = "0xf0"
device i2c 2C on end
end
chip drivers/intel/mipi_camera
register "acpi_hid" = ""OVTI5675""
register "acpi_uid" = "0"
register "acpi_name" = ""CAM1""
register "chip_name" = ""Ov 5675 Camera""
register "device_type" = "INTEL_ACPI_CAMERA_SENSOR"
register "ssdb.lanes_used" = "2"
register "ssdb.link_used" = "1"
register "ssdb.vcm_type" = "0x0C"
register "vcm_name" = ""VCM0""
register "num_freq_entries" = "1"
register "link_freq[0]" = "DEFAULT_LINK_FREQ"
register "remote_name" = ""IPU0""
register "has_power_resource" = "1"
#Controls
register "clk_panel.clks[0].clknum" = "IMGCLKOUT_2"
register "clk_panel.clks[0].freq" = "FREQ_19_2_MHZ"
register "gpio_panel.gpio[0].gpio_num" = "GPP_C3" #PP3300_FCAM_X
register "gpio_panel.gpio[1].gpio_num" = "GPP_A17" #EN_UCAM_PWR
register "gpio_panel.gpio[2].gpio_num" = "GPP_F20" #reset
#_ON
register "on_seq.ops_cnt" = "5"
register "on_seq.ops[0]" = "SEQ_OPS_CLK_ENABLE(0, 0)"
register "on_seq.ops[1]" = "SEQ_OPS_GPIO_ENABLE(0, 5)"
register "on_seq.ops[2]" = "SEQ_OPS_GPIO_ENABLE(1, 5)"
register "on_seq.ops[3]" = "SEQ_OPS_GPIO_DISABLE(2, 5)"
register "on_seq.ops[4]" = "SEQ_OPS_GPIO_ENABLE(2, 5)"
#_OFF
register "off_seq.ops_cnt" = "4"
register "off_seq.ops[0]" = "SEQ_OPS_CLK_DISABLE(0, 0)"
register "off_seq.ops[1]" = "SEQ_OPS_GPIO_DISABLE(2, 0)"
register "off_seq.ops[2]" = "SEQ_OPS_GPIO_DISABLE(1, 0)"
register "off_seq.ops[3]" = "SEQ_OPS_GPIO_DISABLE(0, 0)"
device i2c 36 on
probe UFC UFC_MIPI_5675
end
end
end
device ref i2c3 on end
device ref i2c5 on
@ -538,7 +600,9 @@ chip soc/intel/alderlake
chip drivers/usb/acpi
register "desc" = ""USB2 Camera""
register "type" = "UPC_TYPE_INTERNAL"
device ref usb2_port6 on end
device ref usb2_port6 on
probe UFC UFC_USB
end
end
chip drivers/usb/acpi
register "desc" = ""USB2 Type-A Port (MLB)""