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soc/amd/cezanne: Enable secure counters 

Guybrush uses secure counters to protect against High Definition (HD)
protected content rollback. These secure counters are hosted in TPM
NVRAM. Enable secure counters so that they are defined in PSP verstage.

BUG=b:205261728
TEST=Build and boot to OS in Guybrush. Ensure that the secure counters
are defined successfully in TPM NVRAM.

Change-Id: I6818c6f7905aa2eb815059e23c4f79437593f8ca
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59477
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Rob Barnes <robbarnes@google.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
This commit is contained in:
Karthikeyan Ramasubramanian 2021-11-18 12:28:31 -07:00 committed by Felix Held
parent 4fcf13a51d
commit bef5c40582
1 changed files with 1 additions and 0 deletions
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src/soc/amd/cezanne/Kconfig
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@ -72,6 +72,7 @@ config SOC_SPECIFIC_OPTIONS
select SOC_AMD_COMMON_FSP_PCI
select SSE2
select UDK_2017_BINDING
select VBOOT_DEFINE_WIDEVINE_COUNTERS if VBOOT_STARTS_BEFORE_BOOTBLOCK
select X86_AMD_FIXED_MTRRS
select X86_INIT_NEED_1_SIPI