soc/intel/apollolake: add support for verstage
There previously was no support for building verstage on apollolake. Add that suport by linking in the appropriate modules as well as providing vboot_platform_is_resuming(). The link address for verstage is the same as FSP-M because they would never be in CAR along side each other. Additionally, program the ACPI I/O BAR and enable decoding so sleep state can be determined for early firmware verification. Change-Id: I1a0baab342ac55fd82dbed476abe0063787e3491 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/14972 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com>
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@ -123,6 +123,12 @@ config ROMSTAGE_ADDR
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help
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The base address (in CAR) where romstage should be linked
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config VERSTAGE_ADDR
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hex
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default 0xfef60000
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help
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The base address (in CAR) where verstage should be linked
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config CACHE_MRC_SETTINGS
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bool
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default y
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@ -56,6 +56,12 @@ postcar-y += mmap_boot.c
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postcar-$(CONFIG_SOC_UART_DEBUG) += uart_early.c
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postcar-y += tsc_freq.c
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verstage-y += memmap.c
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verstage-y += mmap_boot.c
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verstage-$(CONFIG_SOC_UART_DEBUG) += uart_early.c
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verstage-y += tsc_freq.c
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verstage-y += pmutil.c
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CPPFLAGS_common += -I$(src)/soc/intel/apollolake/include
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# Since FSP-M runs in CAR we need to relocate it to a specific address
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@ -67,6 +67,12 @@ void asmlinkage bootblock_c_entry(uint32_t tsc_hi, uint32_t tsc_lo)
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pci_write_config32(dev, PCI_BASE_ADDRESS_1, 0);
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pci_write_config16(dev, PCI_COMMAND, PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY);
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/* Decode the ACPI I/O port range for early firmware verification.*/
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dev = PMC_DEV;
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pci_write_config16(dev, PCI_BASE_ADDRESS_4, ACPI_PMIO_BASE);
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pci_write_config16(dev, PCI_COMMAND,
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PCI_COMMAND_IO | PCI_COMMAND_MASTER);
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/* Call lib/bootblock.c main */
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bootblock_main_with_timestamp(((uint64_t)tsc_hi << 32) | tsc_lo);
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}
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@ -26,6 +26,7 @@
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#include <soc/pm.h>
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#include <device/device.h>
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#include <device/pci.h>
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#include <vendorcode/google/chromeos/vboot_common.h>
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static uintptr_t read_pmc_mmio_bar(void)
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{
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@ -336,3 +337,14 @@ int fill_power_state(struct chipset_power_state *ps)
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printk(BIOS_DEBUG, "prev_sleep_state %d\n", ps->prev_sleep_state);
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return ps->prev_sleep_state;
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}
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int vboot_platform_is_resuming(void)
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{
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int typ;
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if (!(inw(ACPI_PMIO_BASE + PM1_STS) & WAK_STS))
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return 0;
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typ = (inl(ACPI_PMIO_BASE + PM1_CNT) & SLP_TYP) >> SLP_TYP_SHIFT;
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return typ == SLP_TYP_S3;
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}
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