soc/intel/apollolake: add support for verstage

There previously was no support for building verstage on apollolake.
Add that suport by linking in the appropriate modules as well as
providing vboot_platform_is_resuming(). The link address for verstage
is the same as FSP-M because they would never be in CAR along side
each other. Additionally, program the ACPI I/O BAR and enable decoding
so sleep state can be determined for early firmware verification.

Change-Id: I1a0baab342ac55fd82dbed476abe0063787e3491
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/14972
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan@google.com>
This commit is contained in:
Aaron Durbin 2016-05-26 11:00:44 -05:00
parent 10221a0e57
commit bef75e7dd9
4 changed files with 30 additions and 0 deletions

View File

@ -123,6 +123,12 @@ config ROMSTAGE_ADDR
help
The base address (in CAR) where romstage should be linked
config VERSTAGE_ADDR
hex
default 0xfef60000
help
The base address (in CAR) where verstage should be linked
config CACHE_MRC_SETTINGS
bool
default y

View File

@ -56,6 +56,12 @@ postcar-y += mmap_boot.c
postcar-$(CONFIG_SOC_UART_DEBUG) += uart_early.c
postcar-y += tsc_freq.c
verstage-y += memmap.c
verstage-y += mmap_boot.c
verstage-$(CONFIG_SOC_UART_DEBUG) += uart_early.c
verstage-y += tsc_freq.c
verstage-y += pmutil.c
CPPFLAGS_common += -I$(src)/soc/intel/apollolake/include
# Since FSP-M runs in CAR we need to relocate it to a specific address

View File

@ -67,6 +67,12 @@ void asmlinkage bootblock_c_entry(uint32_t tsc_hi, uint32_t tsc_lo)
pci_write_config32(dev, PCI_BASE_ADDRESS_1, 0);
pci_write_config16(dev, PCI_COMMAND, PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY);
/* Decode the ACPI I/O port range for early firmware verification.*/
dev = PMC_DEV;
pci_write_config16(dev, PCI_BASE_ADDRESS_4, ACPI_PMIO_BASE);
pci_write_config16(dev, PCI_COMMAND,
PCI_COMMAND_IO | PCI_COMMAND_MASTER);
/* Call lib/bootblock.c main */
bootblock_main_with_timestamp(((uint64_t)tsc_hi << 32) | tsc_lo);
}

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@ -26,6 +26,7 @@
#include <soc/pm.h>
#include <device/device.h>
#include <device/pci.h>
#include <vendorcode/google/chromeos/vboot_common.h>
static uintptr_t read_pmc_mmio_bar(void)
{
@ -336,3 +337,14 @@ int fill_power_state(struct chipset_power_state *ps)
printk(BIOS_DEBUG, "prev_sleep_state %d\n", ps->prev_sleep_state);
return ps->prev_sleep_state;
}
int vboot_platform_is_resuming(void)
{
int typ;
if (!(inw(ACPI_PMIO_BASE + PM1_STS) & WAK_STS))
return 0;
typ = (inl(ACPI_PMIO_BASE + PM1_CNT) & SLP_TYP) >> SLP_TYP_SHIFT;
return typ == SLP_TYP_S3;
}