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mb/google/poppy/variants/nami: Add field to identify single channel DDR

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Variants of Nami need to accommodate single channel DDR.  Will use
GPP_D10 on nami for identification.  GPP_D10 will return 1 when device
is using single channel DDR and 0 when using dual channel DDR.

BUG=b:117194353
BRANCH=None
TEST=dmidecode | grep Channel and make sure that the correct number of
     channels gets returned.

Change-Id: If86ab2c5404c4e818ce496ea935227ab5e51730a
Signed-off-by: Shelley Chen <shchen@google.com>
Reviewed-on: https://review.coreboot.org/29233
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Shelley Chen 2018-10-22 18:07:04 -07:00
parent 6cc937e687
commit bf00401e8a
4 changed files with 16 additions and 3 deletions
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5
src/mainboard/google/poppy/romstage.c
View file

@ -171,7 +171,10 @@ void mainboard_memory_init_params(FSPM_UPD *mupd)
memcpy(&mem_cfg->RcompTarget, p.rcomp_target, p.rcomp_target_size);
mem_cfg->MemorySpdPtr00 = mainboard_get_spd_data(p.type, p.use_sec_spd);
mem_cfg->MemorySpdPtr10 = mem_cfg->MemorySpdPtr00;
if (p.single_channel)
mem_cfg->MemorySpdPtr10 = 0;
else
mem_cfg->MemorySpdPtr10 = mem_cfg->MemorySpdPtr00;
mem_cfg->MemorySpdDataLen = spd_info[p.type].len;
mem_cfg->SaOcSupport = p.enable_sa_oc_support;

3
src/mainboard/google/poppy/variants/baseboard/include/baseboard/variants.h
View file

@ -60,6 +60,9 @@ struct memory_params {
/* The voltage offset applied to the SA in mV. 1000(mV) = Maximum */
uint16_t sa_voltage_offset_val;
/* This would be set to true if only have single DDR channel */
bool single_channel;
};
void variant_memory_params(struct memory_params *p);

7
src/mainboard/google/poppy/variants/nami/gpio.c
View file

@ -179,8 +179,8 @@ static const struct pad_config gpio_table[] = {
PAD_CFG_NC(GPP_D8),
/* D9 : ISH_SPI_CS# ==> HP_IRQ_GPIO */
PAD_CFG_GPI_APIC(GPP_D9, NONE, PLTRST),
/* D10 : ISH_SPI_CLK ==> SPKR_RST_L (unstuffed) */
PAD_CFG_NC(GPP_D10),
/* D10 : ISH_SPI_CLK ==> SINGLE_CHANNEL */
PAD_CFG_GPI_GPIO_DRIVER(GPP_D10, NONE, DEEP),
/* D11 : ISH_SPI_MISO ==> DCI_CLK (debug header) */
PAD_CFG_NC(GPP_D11),
/* D12 : ISH_SPI_MOSI ==> DCI_DATA (debug header) */
@ -370,6 +370,9 @@ static const struct pad_config early_gpio_table[] = {
/* E0 : SATAXPCI0 ==> H1_PCH_INT_ODL */
PAD_CFG_GPI_APIC_INVERT(GPP_E0, NONE, PLTRST),
/* D10 : ISH_SPI_CLK ==> SINGLE_CHANNEL */
PAD_CFG_GPI_GPIO_DRIVER(GPP_D10, 20K_PD, DEEP),
};
const struct pad_config *variant_gpio_table(size_t *num)

4
src/mainboard/google/poppy/variants/nami/memory.c
View file

@ -89,4 +89,8 @@ void variant_memory_params(struct memory_params *p)
else
/* default to DDR4 */
fill_ddr4_memory_params(p);
/* GPP_D10 set to 0 for dual channel and 1 for single channel */
if (gpio_get(GPP_D10))
p->single_channel = 1;
}