diff --git a/Documentation/Intel/Board/board.html b/Documentation/Intel/Board/board.html
index e157780962..1b2d323091 100644
--- a/Documentation/Intel/Board/board.html
+++ b/Documentation/Intel/Board/board.html
@@ -65,7 +65,6 @@
   <li>Configure coreboot build:
     <ol type="A">
       <li>Set LOCALVERSION</li>
-      <li>FLASHMAP_OFFSET = 0x00700000</li>
       <li>Select vendor for the board</li>
       <li>Select the board</li>
       <li>CBFS_SIZE = 0x00100000</li>
@@ -238,4 +237,4 @@
 <hr>
 <p>Modified: 20 February 2016</p>
   </body>
-</html>
\ No newline at end of file
+</html>
diff --git a/src/Kconfig b/src/Kconfig
index e64dd35cab..a11a2da833 100644
--- a/src/Kconfig
+++ b/src/Kconfig
@@ -269,15 +269,6 @@ config NO_STAGE_CACHE
 	 Do not save any component in stage cache for resume path. On resume,
 	 all components would be read back from CBFS again.
 
-config FLASHMAP_OFFSET
-	hex "Flash Map Offset"
-	default 0x00670000 if NORTHBRIDGE_INTEL_SANDYBRIDGE
-	default 0x00610000 if NORTHBRIDGE_INTEL_IVYBRIDGE
-	default CBFS_SIZE if !ARCH_X86
-	default 0
-	help
-	  Offset of flash map in firmware image
-
 # TODO: This doesn't belong here, move to src/arch/x86/Kconfig
 choice
 	prompt "Bootblock behaviour"
diff --git a/src/lib/Makefile.inc b/src/lib/Makefile.inc
index 4c6a395efc..734b517b01 100644
--- a/src/lib/Makefile.inc
+++ b/src/lib/Makefile.inc
@@ -186,6 +186,13 @@ $(call src-to-obj,smm,$(dir)/cbfs.c) : $(obj)/fmap_config.h
 $(call src-to-obj,verstage,$(dir)/cbfs.c) : $(obj)/fmap_config.h
 $(call src-to-obj,postcar,$(dir)/cbfs.c) : $(obj)/fmap_config.h
 
+$(call src-to-obj,bootblock,$(dir)/fmap.c) : $(obj)/fmap_config.h
+$(call src-to-obj,romstage,$(dir)/fmap.c) : $(obj)/fmap_config.h
+$(call src-to-obj,ramstage,$(dir)/fmap.c) : $(obj)/fmap_config.h
+$(call src-to-obj,smm,$(dir)/fmap.c) : $(obj)/fmap_config.h
+$(call src-to-obj,verstage,$(dir)/fmap.c) : $(obj)/fmap_config.h
+$(call src-to-obj,postcar,$(dir)/fmap.c) : $(obj)/fmap_config.h
+
 romstage-y += bootmode.c
 ramstage-y += bootmode.c
 verstage-y += bootmode.c
diff --git a/src/lib/fmap.c b/src/lib/fmap.c
index 54e54ba6b7..bf99037f54 100644
--- a/src/lib/fmap.c
+++ b/src/lib/fmap.c
@@ -21,6 +21,8 @@
 #include <stddef.h>
 #include <string.h>
 
+#include "fmap_config.h"
+
 /*
  * See http://code.google.com/p/flashmap/ for more information on FMAP.
  */
@@ -32,7 +34,7 @@ int find_fmap_directory(struct region_device *fmrd)
 	const struct region_device *boot;
 	struct fmap *fmap;
 	size_t fmap_size;
-	size_t offset = CONFIG_FLASHMAP_OFFSET;
+	size_t offset = FMAP_OFFSET;
 
 	boot_device_init();
 	boot = boot_device_ro();
diff --git a/src/mainboard/google/nyan/Kconfig b/src/mainboard/google/nyan/Kconfig
index a5ecf84cbc..21f42dafc9 100644
--- a/src/mainboard/google/nyan/Kconfig
+++ b/src/mainboard/google/nyan/Kconfig
@@ -82,10 +82,6 @@ config EC_GOOGLE_CHROMEEC_SPI_BUS
 	hex
 	default 1
 
-config FLASHMAP_OFFSET
-	hex
-	default 0x00100000
-
 config DRIVER_TPM_I2C_BUS
 	hex
 	default 0x2
diff --git a/src/mainboard/google/nyan_big/Kconfig b/src/mainboard/google/nyan_big/Kconfig
index fdd40f6661..7af9657e87 100644
--- a/src/mainboard/google/nyan_big/Kconfig
+++ b/src/mainboard/google/nyan_big/Kconfig
@@ -83,10 +83,6 @@ config EC_GOOGLE_CHROMEEC_SPI_BUS
 	hex
 	default 1
 
-config FLASHMAP_OFFSET
-	hex
-	default 0x00100000
-
 config DRIVER_TPM_I2C_BUS
 	hex
 	default 0x2
diff --git a/src/mainboard/google/nyan_blaze/Kconfig b/src/mainboard/google/nyan_blaze/Kconfig
index f28fb24413..9fa99d8a34 100644
--- a/src/mainboard/google/nyan_blaze/Kconfig
+++ b/src/mainboard/google/nyan_blaze/Kconfig
@@ -84,10 +84,6 @@ config EC_GOOGLE_CHROMEEC_SPI_BUS
 	hex
 	default 1
 
-config FLASHMAP_OFFSET
-	hex
-	default 0x00100000
-
 config DRIVER_TPM_I2C_BUS
 	hex
 	default 0x2
diff --git a/src/mainboard/intel/amenia/Kconfig b/src/mainboard/intel/amenia/Kconfig
index b2c1a8ce19..f5460c7b64 100644
--- a/src/mainboard/intel/amenia/Kconfig
+++ b/src/mainboard/intel/amenia/Kconfig
@@ -46,10 +46,6 @@ config IFD_BIOS_START
 	hex
 	default 0x1000
 
-config FLASHMAP_OFFSET
-	hex
-	default 0x200000
-
 config MAX_CPUS
 	int
 	default 8