amdfwtool: Add support of cezanne and renoir
Change-Id: I9e932631e88062b4c385567ed2eff76eda6e10c4 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48525 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Zheng Bao
Hung-Te Lin
parent
a81703c37b
commit
bf29a0d21f
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@ -239,14 +239,27 @@ amd_fw_entry amd_psp_fw_table[] = {
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{ .type = AMD_FW_PSP_SMUSCS, .level = PSP_BOTH },
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{ .type = AMD_PSP_FUSE_CHAIN, .level = PSP_LVL2 },
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{ .type = AMD_DEBUG_UNLOCK, .level = PSP_LVL2 },
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{ .type = AMD_HW_IPCFG, .level = PSP_LVL2 },
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{ .type = AMD_WRAPPED_IKEK, .level = PSP_BOTH },
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{ .type = AMD_TOKEN_UNLOCK, .level = PSP_BOTH },
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{ .type = AMD_SEC_GASKET, .subprog = 0, .level = PSP_BOTH },
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{ .type = AMD_SEC_GASKET, .subprog = 2, .level = PSP_BOTH },
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{ .type = AMD_SEC_GASKET, .subprog = 1, .level = PSP_BOTH },
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{ .type = AMD_MP2_FW, .subprog = 2, .level = PSP_LVL2 },
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{ .type = AMD_MP2_FW, .subprog = 1, .level = PSP_LVL2 },
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{ .type = AMD_MP2_FW, .subprog = 0, .level = PSP_LVL2 },
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{ .type = AMD_DRIVER_ENTRIES, .level = PSP_LVL2 },
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{ .type = AMD_FW_KVM_IMAGE, .level = PSP_LVL2},
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{ .type = AMD_S0I3_DRIVER, .level = PSP_LVL2 },
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{ .type = AMD_VBIOS_BTLOADER, .level = PSP_BOTH },
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{ .type = AMD_FW_TOS_SEC_POLICY, .level = PSP_BOTH },
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{ .type = AMD_FW_USB_PHY, .level = PSP_LVL2 },
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{ .type = AMD_FW_DRTM_TA, .level = PSP_LVL2 },
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{ .type = AMD_FW_KEYDB_BL, .level = PSP_BOTH },
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{ .type = AMD_FW_KEYDB_TOS, .level = PSP_LVL2 },
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{ .type = AMD_FW_DMCU_ERAM, .level = PSP_LVL2 },
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{ .type = AMD_FW_DMCU_ISR, .level = PSP_LVL2 },
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{ .type = AMD_RPMC_NVRAM, .level = PSP_LVL2 },
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{ .type = AMD_ABL0, .level = PSP_BOTH },
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{ .type = AMD_ABL1, .level = PSP_BOTH },
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{ .type = AMD_ABL2, .level = PSP_BOTH },
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@ -271,6 +284,7 @@ amd_fw_entry amd_fw_table[] = {
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};
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amd_bios_entry amd_bios_table[] = {
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{ .type = AMD_BIOS_RTM_PUBKEY, .inst = 0, .level = BDT_BOTH },
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{ .type = AMD_BIOS_APCB, .inst = 0, .level = BDT_BOTH },
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{ .type = AMD_BIOS_APCB, .inst = 1, .level = BDT_BOTH },
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{ .type = AMD_BIOS_APCB, .inst = 2, .level = BDT_BOTH },
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@ -366,7 +380,7 @@ typedef struct _psp_directory_header {
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uint32_t cookie;
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uint32_t checksum;
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uint32_t num_entries;
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uint32_t reserved;
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uint32_t additional_info;
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} __attribute__((packed, aligned(16))) psp_directory_header;
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typedef struct _psp_directory_entry {
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@ -409,7 +423,7 @@ typedef struct _bios_directory_hdr {
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uint32_t cookie;
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uint32_t checksum;
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uint32_t num_entries;
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uint32_t reserved;
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uint32_t additional_info;
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} __attribute__((packed, aligned(16))) bios_directory_hdr;
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typedef struct _bios_directory_entry {
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@ -462,6 +476,7 @@ static void *new_psp_dir(context *ctx, int multi)
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ctx->current = ALIGN(ctx->current, TABLE_ALIGNMENT);
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ptr = BUFF_CURRENT(*ctx);
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((psp_directory_header *)ptr)->additional_info = ctx->current;
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ctx->current += sizeof(psp_directory_header)
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+ MAX_PSP_ENTRIES * sizeof(psp_directory_entry);
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return ptr;
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@ -480,15 +495,20 @@ static void *new_combo_dir(context *ctx)
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}
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#endif
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static void fill_dir_header(void *directory, uint32_t count, uint32_t cookie)
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static void fill_dir_header(void *directory, uint32_t count, uint32_t cookie, context *ctx)
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{
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psp_combo_directory *cdir = directory;
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psp_directory_table *dir = directory;
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bios_directory_table *bdir = directory;
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uint32_t table_size = 0;
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if (!count)
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return;
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/* The table size needs to be 0x1000 aligned. So align the end of table. */
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if (ctx != NULL)
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ctx->current = ALIGN(ctx->current, TABLE_ALIGNMENT);
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switch (cookie) {
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case PSP2_COOKIE:
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/* caller is responsible for lookup mode */
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@ -505,27 +525,38 @@ static void fill_dir_header(void *directory, uint32_t count, uint32_t cookie)
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break;
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case PSP_COOKIE:
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case PSPL2_COOKIE:
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table_size = ctx->current - dir->header.additional_info;
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if ((table_size % TABLE_ALIGNMENT) != 0) {
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fprintf(stderr, "The PSP table size should be 4K aligned\n");
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exit(1);
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}
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dir->header.cookie = cookie;
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dir->header.num_entries = count;
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dir->header.reserved = 0;
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dir->header.additional_info = (table_size / 0x1000) | (1 << 10);
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/* checksum everything that comes after the Checksum field */
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dir->header.checksum = fletcher32(&dir->header.num_entries,
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count * sizeof(psp_directory_entry)
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+ sizeof(dir->header.num_entries)
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+ sizeof(dir->header.reserved));
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+ sizeof(dir->header.additional_info));
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break;
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case BDT1_COOKIE:
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case BDT2_COOKIE:
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table_size = ctx->current - bdir->header.additional_info;
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if ((table_size % TABLE_ALIGNMENT) != 0) {
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fprintf(stderr, "The BIOS table size should be 4K aligned\n");
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exit(1);
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}
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bdir->header.cookie = cookie;
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bdir->header.num_entries = count;
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bdir->header.reserved = 0;
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bdir->header.additional_info = (table_size / 0x1000) | (1 << 10);
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/* checksum everything that comes after the Checksum field */
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bdir->header.checksum = fletcher32(&bdir->header.num_entries,
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count * sizeof(bios_directory_entry)
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+ sizeof(bdir->header.num_entries)
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+ sizeof(bdir->header.reserved));
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+ sizeof(bdir->header.additional_info));
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break;
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}
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}
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static ssize_t copy_blob(void *dest, const char *src_file, size_t room)
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@ -678,7 +709,7 @@ static void integrate_psp_firmwares(context *ctx,
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else
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level = PSP_BOTH;
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ctx->current = ALIGN(ctx->current, BLOB_ALIGNMENT);
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ctx->current = ALIGN(ctx->current, TABLE_ALIGNMENT);
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for (i = 0, count = 0; fw_table[i].type != AMD_FW_INVALID; i++) {
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if (!(fw_table[i].level & level))
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@ -767,7 +798,7 @@ static void integrate_psp_firmwares(context *ctx,
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exit(1);
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}
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fill_dir_header(pspdir, count, cookie);
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fill_dir_header(pspdir, count, cookie, ctx);
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}
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static void *new_bios_dir(context *ctx, int multi)
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@ -784,6 +815,7 @@ static void *new_bios_dir(context *ctx, int multi)
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else
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ctx->current = ALIGN(ctx->current, TABLE_ALIGNMENT);
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ptr = BUFF_CURRENT(*ctx);
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((bios_directory_hdr *) ptr)->additional_info = ctx->current;
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ctx->current += sizeof(bios_directory_hdr)
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+ MAX_BIOS_ENTRIES * sizeof(bios_directory_entry);
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return ptr;
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@ -858,7 +890,7 @@ static void integrate_bios_firmwares(context *ctx,
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else
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level = BDT_BOTH;
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ctx->current = ALIGN(ctx->current, BLOB_ALIGNMENT);
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ctx->current = ALIGN(ctx->current, TABLE_ALIGNMENT);
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for (i = 0, count = 0; fw_table[i].type != AMD_BIOS_INVALID; i++) {
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if (!(fw_table[i].level & level))
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@ -986,7 +1018,6 @@ static void integrate_bios_firmwares(context *ctx,
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fw_table[i].type == AMD_BIOS_APCB_BK)
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ctx->current = ALIGN(
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ctx->current, ERASE_ALIGNMENT);
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bytes = copy_blob(BUFF_CURRENT(*ctx),
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fw_table[i].filename, BUFF_ROOM(*ctx));
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if (bytes <= 0) {
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@ -1028,7 +1059,7 @@ static void integrate_bios_firmwares(context *ctx,
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exit(1);
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}
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fill_dir_header(biosdir, count, cookie);
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fill_dir_header(biosdir, count, cookie, ctx);
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}
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enum {
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@ -1176,6 +1207,7 @@ enum platform {
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PLATFORM_RAVEN,
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PLATFORM_PICASSO,
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PLATFORM_RENOIR,
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PLATFORM_CEZANNE,
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PLATFORM_LUCIENNE,
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};
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@ -1212,6 +1244,7 @@ static int set_efs_table(uint8_t soc_id, embedded_firmware *amd_romsig,
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break;
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case PLATFORM_RENOIR:
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case PLATFORM_LUCIENNE:
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case PLATFORM_CEZANNE:
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amd_romsig->efs_gen.gen = EFS_SECOND_GEN;
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amd_romsig->spi_readmode_f17_mod_30_3f = efs_spi_readmode;
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amd_romsig->spi_fastspeed_f17_mod_30_3f = efs_spi_speed;
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@ -1246,6 +1279,8 @@ static int identify_platform(char *soc_name)
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return PLATFORM_RAVEN;
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else if (!strcasecmp(soc_name, "Picasso"))
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return PLATFORM_PICASSO;
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else if (!strcasecmp(soc_name, "Cezanne"))
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return PLATFORM_CEZANNE;
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else if (!strcasecmp(soc_name, "Renoir"))
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return PLATFORM_RENOIR;
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else if (!strcasecmp(soc_name, "Lucienne"))
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@ -1554,7 +1589,6 @@ int main(int argc, char **argv)
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return 1;
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}
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}
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ctx.rom = malloc(ctx.rom_size);
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if (!ctx.rom) {
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fprintf(stderr, "Error: Failed to allocate memory\n");
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@ -1621,7 +1655,7 @@ int main(int argc, char **argv)
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combo_dir->entries[0].lvl2_addr = BUFF_TO_RUN(ctx, pspdir);
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combo_dir->header.lookup = 1;
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fill_dir_header(combo_dir, 1, PSP2_COOKIE);
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fill_dir_header(combo_dir, 1, PSP2_COOKIE, NULL);
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#endif
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if (have_bios_tables(amd_bios_table)) {
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@ -1642,7 +1676,19 @@ int main(int argc, char **argv)
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integrate_bios_firmwares(&ctx, biosdir, 0,
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amd_bios_table, BDT1_COOKIE);
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}
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switch (soc_id) {
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case PLATFORM_RENOIR:
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case PLATFORM_LUCIENNE:
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case PLATFORM_CEZANNE:
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amd_romsig->bios3_entry = BUFF_TO_RUN(ctx, biosdir);
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break;
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case PLATFORM_STONEYRIDGE:
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case PLATFORM_RAVEN:
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case PLATFORM_PICASSO:
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default:
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amd_romsig->bios1_entry = BUFF_TO_RUN(ctx, biosdir);
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break;
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}
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}
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/* Free the filename. */
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@ -26,11 +26,13 @@ typedef enum _amd_fw_type {
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AMD_PSP_FUSE_CHAIN = 11,
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AMD_FW_PSP_SMUSCS = 95,
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AMD_DEBUG_UNLOCK = 0x13,
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AMD_HW_IPCFG = 0x20,
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AMD_WRAPPED_IKEK = 0x21,
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AMD_TOKEN_UNLOCK = 0x22,
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AMD_SEC_GASKET = 0x24,
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AMD_MP2_FW = 0x25,
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AMD_DRIVER_ENTRIES = 0x28,
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AMD_FW_KVM_IMAGE = 0x29,
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AMD_S0I3_DRIVER = 0x2d,
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AMD_ABL0 = 0x30,
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AMD_ABL1 = 0x31,
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@ -41,9 +43,18 @@ typedef enum _amd_fw_type {
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AMD_ABL6 = 0x36,
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AMD_ABL7 = 0x37,
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AMD_FW_PSP_WHITELIST = 0x3a,
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AMD_VBIOS_BTLOADER = 0x3c,
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AMD_FW_L2_PTR = 0x40,
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AMD_FW_USB_PHY = 0x44,
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AMD_FW_TOS_SEC_POLICY = 0x45,
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AMD_FW_DRTM_TA = 0x47,
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AMD_FW_KEYDB_BL = 0x50,
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AMD_FW_KEYDB_TOS = 0x51,
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AMD_FW_PSP_VERSTAGE = 0x52,
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AMD_FW_VERSTAGE_SIG = 0x53,
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AMD_RPMC_NVRAM = 0x54,
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AMD_FW_DMCU_ERAM = 0x58,
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AMD_FW_DMCU_ISR = 0x59,
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AMD_FW_IMC = 0x200, /* Large enough to be larger than the top BHD entry type. */
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AMD_FW_GEC,
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AMD_FW_XHCI,
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@ -52,6 +63,7 @@ typedef enum _amd_fw_type {
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} amd_fw_type;
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typedef enum _amd_bios_type {
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AMD_BIOS_RTM_PUBKEY = 5,
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AMD_BIOS_APCB = 0x60,
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AMD_BIOS_APOB = 0x61,
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AMD_BIOS_BIN = 0x62,
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@ -90,6 +90,9 @@ static uint8_t find_register_fw_filename_psp_dir(char *fw_name, char *filename,
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} else if (strcmp(fw_name, "PSP_SMUFW1_SUB0_FILE") == 0) {
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fw_type = AMD_FW_PSP_SMU_FIRMWARE;
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subprog = 0;
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} else if (strcmp(fw_name, "PSP_HW_IPCFG_FILE") == 0) {
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fw_type = AMD_HW_IPCFG;
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subprog = 0;
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} else if (strcmp(fw_name, "PSP_SMUFW1_SUB1_FILE") == 0) {
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fw_type = AMD_FW_PSP_SMU_FIRMWARE;
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subprog = 1;
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@ -167,12 +170,22 @@ static uint8_t find_register_fw_filename_psp_dir(char *fw_name, char *filename,
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} else if (strcmp(fw_name, "PSP_IKEK_FILE") == 0) {
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fw_type = AMD_WRAPPED_IKEK;
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subprog = 0;
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} else if (strcmp(fw_name, "PSP_SECG0_FILE") == 0) {
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fw_type = AMD_SEC_GASKET;
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subprog = 0;
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} else if (strcmp(fw_name, "PSP_SECG1_FILE") == 0) {
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fw_type = AMD_SEC_GASKET;
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subprog = 1;
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} else if (strcmp(fw_name, "PSP_SECG2_FILE") == 0) {
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fw_type = AMD_SEC_GASKET;
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subprog = 2;
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} else if (strcmp(fw_name, "PSP_MP2FW0_FILE") == 0) {
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if (cb_config->load_mp2_fw == 1) {
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fw_type = AMD_MP2_FW;
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subprog = 0;
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} else {
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fw_type = AMD_FW_SKIP;
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}
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} else if (strcmp(fw_name, "PSP_MP2FW1_FILE") == 0) {
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if (cb_config->load_mp2_fw == 1) {
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fw_type = AMD_MP2_FW;
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@ -197,10 +210,44 @@ static uint8_t find_register_fw_filename_psp_dir(char *fw_name, char *filename,
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} else {
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fw_type = AMD_FW_SKIP;
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}
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} else if (strcmp(fw_name, "AMD_DRIVER_ENTRIES") == 0) {
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fw_type = AMD_DRIVER_ENTRIES;
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subprog = 0;
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} else if (strcmp(fw_name, "VBIOS_BTLOADER_FILE") == 0) {
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fw_type = AMD_VBIOS_BTLOADER;
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subprog = 0;
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} else if (strcmp(fw_name, "SECURE_POLICY_L1_FILE") == 0) {
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fw_type = AMD_FW_TOS_SEC_POLICY;
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subprog = 0;
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} else if (strcmp(fw_name, "UNIFIEDUSB_FILE") == 0) {
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fw_type = AMD_FW_USB_PHY;
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subprog = 0;
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} else if (strcmp(fw_name, "DRTMTA_FILE") == 0) {
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fw_type = AMD_FW_DRTM_TA;
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subprog = 0;
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} else if (strcmp(fw_name, "KEYDBBL_FILE") == 0) {
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fw_type = AMD_FW_KEYDB_BL;
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subprog = 0;
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} else if (strcmp(fw_name, "KEYDB_TOS_FILE") == 0) {
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fw_type = AMD_FW_KEYDB_TOS;
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subprog = 0;
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} else if (strcmp(fw_name, "DMCUERAMDCN21_FILE") == 0) {
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fw_type = AMD_FW_DMCU_ERAM;
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subprog = 0;
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} else if (strcmp(fw_name, "DMCUINTVECTORSDCN21_FILE") == 0) {
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fw_type = AMD_FW_DMCU_ISR;
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subprog = 0;
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} else if (strcmp(fw_name, "PSP_KVM_ENGINE_DUMMY_FILE") == 0) {
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fw_type = AMD_FW_KVM_IMAGE;
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subprog = 0;
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} else if (strcmp(fw_name, "RPMC_FILE") == 0) {
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fw_type = AMD_RPMC_NVRAM;
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subprog = 0;
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} else {
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fw_type = AMD_FW_INVALID;
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/* TODO: Add more */
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}
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/* Search and fill the filename */
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psp_tableptr = &amd_psp_fw_table[0];
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if (fw_type != AMD_FW_SKIP && fw_type != AMD_FW_INVALID) {
|
||||
|
|
@ -261,6 +308,10 @@ static uint8_t find_register_fw_filename_bios_dir(char *fw_name, char *filename,
|
|||
fw_type = AMD_BIOS_PMUD;
|
||||
subprog = 1;
|
||||
instance = 4;
|
||||
} else if (strcmp(fw_name, "RTM_PUBKEY_FILE") == 0) {
|
||||
fw_type = AMD_BIOS_RTM_PUBKEY;
|
||||
subprog = 0;
|
||||
instance = 0;
|
||||
} else if (strcmp(fw_name, "PSP_MP2CFG_FILE") == 0) {
|
||||
if (cb_config->load_mp2_fw == 1) {
|
||||
fw_type = AMD_BIOS_MP2_CFG;
|
||||
|
|
|
|||
Loading…
Reference in New Issue