mb/google/brya/var/skolas: Adjust I2C3 CLK to meet 400 kHz

Fine tune I2C3 clock frequency under the 400 kHz. From 402.7 kHz to
382.9 kHz.

BUG=b:255505160
BRANCH=firmware-brya-14505.B
TEST=FW_NAME="skolas" emerge-brya coreboot chromeos-bootimage
     measure by scope with skolas

Signed-off-by: AlanKY Lee <alanky_lee@compal.corp-partner.google.com>
Change-Id: Ib6c3f895751387256378964ec76be45a4fcbba4e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68906
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>

src/mainboard/google/brya/variants/skolas/overridetree.cb

@@ -95,7 +95,7 @@ chip soc/intel/alderlake
 		},
 		.i2c[3] = {
 			.speed = I2C_SPEED_FAST,
-			.rise_time_ns = 650,
+			.rise_time_ns = 600,
 			.fall_time_ns = 400,
 			.data_hold_time_ns = 50,
 		},