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mb/intel/adlrvp: Program GPIO for M.2 PCH SSD 

This patch programs GPIO for PCH SSD Power Enable (GPP_D16) and Port
Detect (GPP_A12) as per schematics.

TEST=Able to build and boot ADL RVP.

Change-Id: I015e46bdf25437c6b196deb3e610bc1b58726070
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46417
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
This commit is contained in:
Subrata Banik 2020-10-14 21:53:59 +05:30
parent e0ce60c744
commit bf38d58420
1 changed files with 4 additions and 0 deletions
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4
src/mainboard/intel/adlrvp/variants/adlrvp_p/gpio.c
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@ -70,7 +70,11 @@ static const struct pad_config gpio_table[] = {
PAD_CFG_GPO(GPP_H1, 1, PLTRST), PAD_CFG_GPO(GPP_H1, 1, PLTRST),
/* Sata direct Power */ /* Sata direct Power */
PAD_CFG_GPO(GPP_B4, 1, PLTRST), PAD_CFG_GPO(GPP_B4, 1, PLTRST),
/* M.2_PCH_SSD_PWREN */
PAD_CFG_GPO(GPP_D16, 1, PLTRST),
/* M.2_SSD_PDET_R */
PAD_CFG_NF(GPP_A12, NONE, DEEP, NF1),
/* THC0 SPI1 CLK */ /* THC0 SPI1 CLK */
PAD_CFG_NF(GPP_E11, NONE, DEEP, NF2), PAD_CFG_NF(GPP_E11, NONE, DEEP, NF2),
/* THC0 SPI1 IO 1 */ /* THC0 SPI1 IO 1 */