GNUBoot
/
coreboot-kgpe-d16
2
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

mb/google/guybrush/var/dewatt: Update unused GPIO pins 

According to H/W schematics,
fingerprint, SD controller, WWAN/LTE and PEN modules are not stuffed and hence the following GPIOs are marked as not connected:
GPIO_3 : TP247
GPIO_4 : TP218
GPIO_5 : TP220
GPIO_8 : TP245
GPIO_11: TP244
GPIO_17: TP194
GPIO_18: TP195
GPIO_21: TP243
GPIO_24: TP196
GPIO_31: TP50
GPIO_42: TP219
GPIO_69: TP217
GPIO_115: TP235
GPIO_116: TP205
GPIO_140: TP226
GPIO_142: TP225
GPIO_144: TP227

BUG=b:204155627
TEST=emerge-guybrush coreboot chromeos-bootimage

Signed-off-by: Kenneth Chan <kenneth.chan@quanta.corp-partner.google.com>
Change-Id: I552fd6af1cd827e4e41be1a954bf95c3afbb6a86
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60782
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
This commit is contained in:
Kenneth Chan 2022-01-05 11:14:59 +08:00 committed by Karthik Ramasubramanian
parent 8d092aa5d9
commit bf4592743c
3 changed files with 98 additions and 1 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

5
src/mainboard/google/guybrush/variants/dewatt/Makefile.inc
View File

@ -1,3 +1,8 @@
# SPDX-License-Identifier: GPL-2.0-or-later
bootblock-y += gpio.c
romstage-y += gpio.c
ramstage-y += gpio.c
verstage-y += gpio.c
subdirs-y += ./memory

91
src/mainboard/google/guybrush/variants/dewatt/gpio.c Normal file
View File

@ -0,0 +1,91 @@
/* SPDX-License-Identifier: GPL-2.0-or-later */
#include <baseboard/gpio.h>
#include <baseboard/variants.h>
#include <boardid.h>
#include <gpio.h>
#include <soc/gpio.h>
#include <baseboard/variants.h>
/* This table is used by guybrush variant */
static const struct soc_amd_gpio override_ramstage_gpio_table[] = {
/* Unused TP247*/
PAD_NC(GPIO_3),
/* Unused TP218*/
PAD_NC(GPIO_4),
/* Unused TP245*/
PAD_NC(GPIO_8),
/* Unused TP244*/
PAD_NC(GPIO_11),
/* Unused TP194*/
PAD_NC(GPIO_17),
/* Unused TP195*/
PAD_NC(GPIO_18),
/* Unused TP243*/
PAD_NC(GPIO_21),
/* Unused TP196*/
PAD_NC(GPIO_24),
/* Unused TP219*/
PAD_NC(GPIO_42),
/* Unused TP217*/
PAD_NC(GPIO_69),
/* Unused TP235*/
PAD_NC(GPIO_115),
/* Unused TP205*/
PAD_NC(GPIO_116),
/* Unused TP226*/
PAD_NC(GPIO_140),
/* Unused TP225*/
PAD_NC(GPIO_142),
/* Unused TP227*/
PAD_NC(GPIO_144),
};
static const struct soc_amd_gpio override_early_gpio_table[] = {
/* Unused TP245*/
PAD_NC(GPIO_8),
/* Unused TP195*/
PAD_NC(GPIO_18),
/* Unused TP196*/
PAD_NC(GPIO_24),
/* Unused TP217*/
PAD_NC(GPIO_69),
};
/* This table is used by guybrush variant */
static const struct soc_amd_gpio override_pcie_gpio_table[] = {
/* Unused TP195*/
PAD_NC(GPIO_18),
/* Unused TP217*/
PAD_NC(GPIO_69),
};
static const struct soc_amd_gpio override_bootblock_gpio_table[] = {
/* Unused TP196*/
PAD_NC(GPIO_24),
};
const struct soc_amd_gpio *variant_override_gpio_table(size_t *size)
{
*size = ARRAY_SIZE(override_ramstage_gpio_table);
return override_ramstage_gpio_table;
}
const struct soc_amd_gpio *variant_early_override_gpio_table(size_t *size)
{
*size = ARRAY_SIZE(override_early_gpio_table);
return override_early_gpio_table;
}
const struct soc_amd_gpio *variant_pcie_override_gpio_table(size_t *size)
{
*size = ARRAY_SIZE(override_pcie_gpio_table);
return override_pcie_gpio_table;
}
const struct soc_amd_gpio *variant_bootblock_override_gpio_table(size_t *size)
{
*size = ARRAY_SIZE(override_bootblock_gpio_table);
return override_bootblock_gpio_table;
}

3
src/mainboard/google/guybrush/variants/dewatt/overridetree.cb
View File

@ -2,7 +2,8 @@
chip soc/amd/cezanne
device domain 0 on
device ref gpp_bridge_1 off end # no SD
device ref gpp_bridge_2 off end # no WWAN
end # domain
register "slow_ppt_limit_mW" = "25000"