From bf46ba5adbd7cec13986d8b6584a2a14bfc9109e Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Michael=20Niew=C3=B6hner?= Date: Wed, 15 Sep 2021 16:42:17 +0200 Subject: [PATCH] soc/intel/xeon_sp: correct wrong gpio register base offsets MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Reference: Intel doc# 633935-005 and 547817 rev1.5. Change-Id: I38c20288a9839f8c3cf895f7b49941387bdca5e2 Signed-off-by: Michael Niewöhner Reviewed-on: https://review.coreboot.org/c/coreboot/+/57677 Tested-by: build bot (Jenkins) Reviewed-by: David Hendricks Reviewed-by: Lance Zhao Reviewed-by: Jonathan Zhang --- .../intel/xeon_sp/include/soc/lewisburg_pch_gpio_defs.h | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/src/soc/intel/xeon_sp/include/soc/lewisburg_pch_gpio_defs.h b/src/soc/intel/xeon_sp/include/soc/lewisburg_pch_gpio_defs.h index 2ad5fba38b..2049c3fcaf 100644 --- a/src/soc/intel/xeon_sp/include/soc/lewisburg_pch_gpio_defs.h +++ b/src/soc/intel/xeon_sp/include/soc/lewisburg_pch_gpio_defs.h @@ -656,12 +656,12 @@ #define GPIO_DRIVER_IRQ_ROUTE_IRQ14 0 #define GPIO_DRIVER_IRQ_ROUTE_IRQ15 8 -#define HOSTSW_OWN_REG_0 0xd0 +#define HOSTSW_OWN_REG_0 0x80 #define PAD_CFG_BASE 0x400 #define GPI_INT_STS_0 0x100 -#define GPI_INT_EN_0 0x120 -#define GPI_SMI_STS_0 0x180 -#define GPI_SMI_EN_0 0x1a0 +#define GPI_INT_EN_0 0x110 +#define GPI_SMI_STS_0 0x140 +#define GPI_SMI_EN_0 0x150 #define GPI_NMI_STS_0 0x160 #define GPI_NMI_EN_0 0x170