rockchip: rk3399: support saradc

This patch add functions to configure saradc clk and get
saradc's raw value for each channel.

Currently add saradc to ramstage.

Please refer to TRM V0.3 Part 2 Chapter 18 for this IP.

BRANCH=none
BUG=chrome-os-partner:51537
TEST=on kevin board, get the raw value 61 for channel 0,
     measure the ADC_IN0 as 0.109V,
     61.0/1024 = 0.05957  0.109V/1.8V = 0.06056

Change-Id: Ic198b2a964ccf8bb687441f0e2702665402fff6e
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: bc400316de2d75eccad3990a4187bf2dc49a844a
Original-Change-Id: I542430ed97bd27f9bfcec89b1d703d9fa390d4e0
Original-Signed-off-by: Lin Huang <hl@rock-chips.com>
Original-Signed-off-by: Shunqian Zheng <zhengsq@rock-chips.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/334177
Original-Commit-Ready: Vadim Bendebury <vbendeb@chromium.org>
Original-Tested-by: Vadim Bendebury <vbendeb@chromium.org>
Original-Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://review.coreboot.org/14720
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

src/soc/rockchip/rk3399/Makefile.inc

@@ -55,6 +55,7 @@ ramstage-y += clock.c
 ramstage-y += ../common/gpio.c
 ramstage-y += gpio.c
 ramstage-y += ../common/i2c.c
+ramstage-y += saradc.c
 ramstage-y += soc.c
 ramstage-y += timer.c
 

src/soc/rockchip/rk3399/clock.c

@@ -155,6 +155,10 @@ enum {
 	HCLK_PERILP1_DIV_CON_MASK	= 0x1f,
 	HCLK_PERILP1_DIV_CON_SHIFT	= 0,
 
+	/* CLKSEL_CON26 */
+	CLK_SARADC_DIV_CON_MASK		= 0xff,
+	CLK_SARADC_DIV_CON_SHIFT	= 8,
+
 	/* CLKSEL_CON58 */
 	CLK_SPI_PLL_SEL_MASK		= 1,
 	CLK_SPI_PLL_SEL_CPLL		= 0,
@@ -575,3 +579,17 @@ uint32_t rkclk_i2c_clock_for_bus(unsigned bus)
 
 	return freq;
 }
+
+void rkclk_configure_saradc(unsigned int hz)
+{
+	int src_clk_div;
+
+	/* saradc src clk from 24MHz */
+	src_clk_div = 24 * MHz / hz;
+	assert((src_clk_div - 1 < 255) && (src_clk_div * hz == 24 * MHz));
+
+	write32(&cru_ptr->clksel_con[26],
+		RK_CLRSETBITS(CLK_SARADC_DIV_CON_MASK <<
+						CLK_SARADC_DIV_CON_SHIFT,
+			      (src_clk_div - 1) << CLK_SARADC_DIV_CON_SHIFT));
+}

src/soc/rockchip/rk3399/include/soc/clock.h

@@ -105,6 +105,7 @@ enum apll_l_frequencies {
 void rkclk_init(void);
 void rkclk_configure_cpu(enum apll_l_frequencies apll_l_freq);
 void rkclk_configure_ddr(unsigned int hz);
+void rkclk_configure_saradc(unsigned int hz);
 void rkclk_configure_spi(unsigned int bus, unsigned int hz);
 void rkclk_ddr_reset(u32 ch, u32 ctl, u32 phy);
 uint32_t rkclk_i2c_clock_for_bus(unsigned bus);

src/soc/rockchip/rk3399/include/soc/saradc.h

@@ -0,0 +1,21 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2016 Rockchip Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#ifndef __SOC_ROCKCHIP_RK3399_SARADC_H__
+#define __SOC_ROCKCHIP_RK3399_SARADC_H__
+
+u32 get_saradc_value(u32 chn);
+#endif

src/soc/rockchip/rk3399/saradc.c

@@ -0,0 +1,93 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2016 Rockchip Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#include <arch/io.h>
+#include <assert.h>
+#include <console/console.h>
+#include <delay.h>
+#include <soc/clock.h>
+#include <soc/saradc.h>
+#include <stdint.h>
+#include <stdlib.h>
+#include <timer.h>
+
+struct rk3399_saradc_regs {
+	u32 data;
+	u32 stas;
+	u32 ctrl;
+	u32 dly_pu_soc;
+};
+check_member(rk3399_saradc_regs, dly_pu_soc, 0xc);
+
+struct rk3399_saradc_regs *rk3399_saradc = (void *)SARADC_BASE;
+
+/* SARADC_STAS: conversion done */
+#define ADC_STOP	0
+
+/* SARADC_CTRL */
+#define INT_EN			(1 << 5)
+#define ADC_PWR_CTRL		(1 << 3)
+#define ADC_CHN_SEL_MASK	7
+#define ADC_CHN_SEL_SHIFT	0
+
+/* SARADC_DATA, 10[0:9] bits */
+#define DATA_MASK		0x3FF
+
+/* The max clk is 13 MHz, we also recommended that
+ * the sample rate(=clk/13) should be > 500KHz.
+ * So choose 8MHz, that 8MHz/13 = 615.38KHz > 500KHz.
+ */
+#define SARADC_HZ		(8*MHz)
+
+/* TRM(V0.3 Part 1 Page 366) said there is a delay between
+ * power up and start command, default value is 2 src clk.
+ * Let delay 2 src clk here, in ns(udelay).
+ */
+#define SARADC_DELAY_PU		(1 * 1000 * 1000 * 1000 / SARADC_HZ * 2)
+
+#define SARADC_MAX_CHANNEL	6
+
+u32 get_saradc_value(u32 chn)
+{
+	u32 adc_value;
+	struct stopwatch sw;
+
+	assert(chn < SARADC_MAX_CHANNEL);
+	rkclk_configure_saradc(SARADC_HZ);
+
+	/* power down adc converter */
+	clrbits_le32(&rk3399_saradc->ctrl, ADC_PWR_CTRL);
+
+	/* select channel */
+	clrsetbits_le32(&rk3399_saradc->ctrl,
+			ADC_CHN_SEL_MASK << ADC_CHN_SEL_SHIFT,
+			chn << ADC_CHN_SEL_SHIFT);
+
+	/* power up */
+	setbits_le32(&rk3399_saradc->ctrl, ADC_PWR_CTRL);
+
+	udelay(SARADC_DELAY_PU);
+
+	stopwatch_init_msecs_expire(&sw, 10);
+	do {
+		if (read32(&rk3399_saradc->stas) == ADC_STOP) {
+			adc_value = read32(&rk3399_saradc->data) & DATA_MASK;
+			return adc_value;
+		}
+	} while (!stopwatch_expired(&sw));
+
+	return -1;
+}