nb/intel/x4x: Move boilerplate romstage to a common location
This adds 3 mb romstage callbacks: - void mb_lpc_setup(void) to be used to set up the superio - void mb_get_spd_map(u8 spd_map[4]) to get I2C addresses of SPDs - (optional)mb_pre_raminit_setup(int s3_resume) to set up mainboard specific things before the raminit. Change-Id: Ic3b838856b3076ed05eeeea7c0656c2078462272 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36758 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
parent
dc7b2de88b
commit
bf53acca5e
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@ -16,11 +16,7 @@
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*/
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#include <device/pnp_ops.h>
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#include <device/pci_ops.h>
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#include <console/console.h>
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#include <arch/romstage.h>
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#include <northbridge/intel/x4x/x4x.h>
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#include <southbridge/intel/common/pmclib.h>
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#include <southbridge/intel/i82801gx/i82801gx.h>
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#include <superio/nuvoton/common/nuvoton.h>
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#include <superio/nuvoton/nct6776/nct6776.h>
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@ -30,9 +26,8 @@
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#define SERIAL_DEV_R2 PNP_DEV(0x2e, NCT6776_SP1)
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#define SERIAL_DEV_R1 PNP_DEV(0x2e, W83627DHG_SP1)
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#define SUPERIO_DEV PNP_DEV(0x2e, 0)
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#define LPC_DEV PCI_DEV(0, 0x1f, 0)
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static void mb_lpc_setup(void)
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void mb_lpc_setup(void)
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{
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/* Set GPIOs on superio, enable UART */
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if (CONFIG(SUPERIO_NUVOTON_NCT6776)) {
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@ -53,34 +48,8 @@ static void mb_lpc_setup(void)
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RCBA16(D29IR) = 0x0237;
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}
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void mainboard_romstage_entry(void)
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void mb_get_spd_map(u8 spd_map[4])
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{
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// ch0 ch1
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const u8 spd_addrmap[4] = { 0x50, 0, 0x52, 0 };
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u8 boot_path = 0;
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u8 s3_resume;
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/* Set southbridge and Super I/O GPIOs. */
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i82801gx_lpc_setup();
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mb_lpc_setup();
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console_init();
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enable_smbus();
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i82801gx_early_init();
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x4x_early_init();
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s3_resume = southbridge_detect_s3_resume();
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if (s3_resume)
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boot_path = BOOT_PATH_RESUME;
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if (MCHBAR32(PMSTS_MCHBAR) & PMSTS_WARM_RESET)
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boot_path = BOOT_PATH_WARM_RESET;
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sdram_initialize(boot_path, spd_addrmap);
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x4x_late_init(s3_resume);
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printk(BIOS_DEBUG, "x4x late init complete\n");
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spd_map[0] = 0x50;
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spd_map[2] = 0x52;
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}
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@ -14,57 +14,27 @@
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* GNU General Public License for more details.
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*/
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#include <device/pci_ops.h>
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#include <console/console.h>
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#include <southbridge/intel/i82801jx/i82801jx.h>
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#include <southbridge/intel/common/pmclib.h>
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#include <northbridge/intel/x4x/x4x.h>
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#include <arch/romstage.h>
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#include <superio/winbond/w83667hg-a/w83667hg-a.h>
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#include <superio/winbond/common/winbond.h>
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#define SERIAL_DEV PNP_DEV(0x2e, W83667HG_A_SP1)
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#define LPC_DEV PCI_DEV(0, 0x1f, 0)
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/* Early mainboard specific GPIO setup.
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* We should use standard gpio.h eventually
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*/
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static void mb_misc_rcba(void)
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void mb_lpc_setup(void)
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{
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/* TODO? */
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RCBA32(RCBA_CG) = 0xbf7f001f;
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RCBA32(0x3430) = 0x00000002;
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RCBA32(0x3f00) = 0x00000038;
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}
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void mainboard_romstage_entry(void)
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{
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const u8 spd_addrmap[4] = { 0x50, 0x51, 0x52, 0x53 };
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u8 boot_path = 0;
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u8 s3_resume;
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/* Set southbridge and Super I/O GPIOs. */
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i82801jx_lpc_setup();
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mb_misc_rcba();
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winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
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console_init();
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enable_smbus();
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i82801jx_early_init();
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x4x_early_init();
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s3_resume = southbridge_detect_s3_resume();
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if (s3_resume)
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boot_path = BOOT_PATH_RESUME;
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if (MCHBAR32(PMSTS_MCHBAR) & PMSTS_WARM_RESET)
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boot_path = BOOT_PATH_WARM_RESET;
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sdram_initialize(boot_path, spd_addrmap);
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x4x_late_init(s3_resume);
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printk(BIOS_DEBUG, "x4x late init complete\n");
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}
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void mb_get_spd_map(u8 spd_map[4])
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{
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spd_map[0] = 0x50;
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spd_map[1] = 0x51;
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spd_map[2] = 0x52;
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spd_map[3] = 0x53;
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}
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@ -12,22 +12,22 @@
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* GNU General Public License for more details.
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*/
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#include <device/pci_ops.h>
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#include <device/pnp_ops.h>
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#include <console/console.h>
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#include <southbridge/intel/i82801jx/i82801jx.h>
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#include <southbridge/intel/common/pmclib.h>
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#include <northbridge/intel/x4x/x4x.h>
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#include <cpu/x86/msr.h>
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#include <cpu/intel/speedstep.h>
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#include <arch/romstage.h>
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#include <cf9_reset.h>
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#include <superio/winbond/w83627dhg/w83627dhg.h>
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#include <superio/winbond/common/winbond.h>
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#define SERIAL_DEV PNP_DEV(0x2e, W83627DHG_SP1)
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#define GPIO_DEV PNP_DEV(0x2e, W83627DHG_GPIO2345_V)
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#define LPC_DEV PCI_DEV(0, 0x1f, 0)
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void mb_lpc_setup(void)
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{
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winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
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}
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static u8 msr_get_fsb(void)
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{
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return need_reset;
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}
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void mainboard_romstage_entry(void)
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void mb_pre_raminit_setup(int s3_resume)
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{
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/* This board has first dimm slot of each channel hooked up to
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rank0 and rank1, while the second dimm slot is only connected
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to rank1. The raminit does not support such setups
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const u8 spd_addrmap[4] = { 0x50, 0x51, 0x52, 0x53 }; */
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const u8 spd_addrmap[4] = { 0x50, 0, 0x52, 0 };
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u8 boot_path = 0;
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u8 s3_resume;
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/* Set southbridge and Super I/O GPIOs. */
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i82801jx_lpc_setup();
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winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
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console_init();
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enable_smbus();
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i82801jx_early_init();
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x4x_early_init();
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s3_resume = southbridge_detect_s3_resume();
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if (s3_resume)
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boot_path = BOOT_PATH_RESUME;
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if (MCHBAR32(PMSTS_MCHBAR) & PMSTS_WARM_RESET)
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boot_path = BOOT_PATH_WARM_RESET;
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if (!s3_resume && setup_sio_gpio()) {
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printk(BIOS_DEBUG, "Needs reset to configure CPU BSEL straps\n");
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full_reset();
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}
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sdram_initialize(boot_path, spd_addrmap);
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x4x_late_init(s3_resume);
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printk(BIOS_DEBUG, "x4x late init complete\n");
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}
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void mb_get_spd_map(u8 spd_map[4])
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{
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/* This board has first dimm slot of each channel hooked up to
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rank0 and rank1, while the second dimm slot is only connected
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to rank1. The raminit does not support such setups. So only the
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first dimms of each channel are used. */
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spd_map[0] = 0x50;
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spd_map[2] = 0x52;
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}
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#include <cf9_reset.h>
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#include <device/pnp_ops.h>
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#include <device/pci_ops.h>
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#include <console/console.h>
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#include <arch/romstage.h>
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#include <cpu/intel/speedstep.h>
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#include <cpu/x86/msr.h>
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#include <northbridge/intel/x4x/x4x.h>
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#include <southbridge/intel/common/pmclib.h>
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#include <southbridge/intel/i82801gx/i82801gx.h>
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#include <superio/winbond/common/winbond.h>
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#include <superio/winbond/w83627dhg/w83627dhg.h>
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#define SERIAL_DEV PNP_DEV(0x2e, W83627DHG_SP1)
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#define GPIO_DEV PNP_DEV(0x2e, W83627DHG_GPIO2345_V)
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#define LPC_DEV PCI_DEV(0, 0x1f, 0)
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void mb_lpc_setup(void)
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{
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winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
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}
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static u8 msr_get_fsb(void)
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{
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return need_reset;
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}
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void mainboard_romstage_entry(void)
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void mb_pre_raminit_setup(int s3_resume)
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{
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// ch0 ch1
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const u8 spd_addrmap[4] = { 0x50, 0, 0x52, 0 };
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u8 boot_path = 0;
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u8 s3_resume;
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/* Set southbridge and Super I/O GPIOs. */
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i82801gx_lpc_setup();
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winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
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console_init();
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enable_smbus();
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i82801gx_early_init();
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x4x_early_init();
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s3_resume = southbridge_detect_s3_resume();
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if (s3_resume)
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boot_path = BOOT_PATH_RESUME;
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if (MCHBAR32(PMSTS_MCHBAR) & PMSTS_WARM_RESET)
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boot_path = BOOT_PATH_WARM_RESET;
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if (!s3_resume && setup_sio_gpio()) {
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printk(BIOS_DEBUG,
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"Needs reset to configure CPU BSEL straps\n");
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printk(BIOS_DEBUG, "Needs reset to configure CPU BSEL straps\n");
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full_reset();
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}
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sdram_initialize(boot_path, spd_addrmap);
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x4x_late_init(s3_resume);
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printk(BIOS_DEBUG, "x4x late init complete\n");
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}
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void mb_get_spd_map(u8 spd_map[4])
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{
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spd_map[0] = 0x50;
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spd_map[2] = 0x52;
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}
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* GNU General Public License for more details.
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*/
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#include <console/console.h>
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#include <arch/romstage.h>
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#include <device/pci_ops.h>
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#include <northbridge/intel/x4x/x4x.h>
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#include <southbridge/intel/common/pmclib.h>
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#include <southbridge/intel/i82801gx/i82801gx.h>
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#include <superio/ite/common/ite.h>
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#include <superio/ite/it8720f/it8720f.h>
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#define LPC_DEV PCI_DEV(0, 0x1f, 0)
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#define SERIAL_DEV PNP_DEV(0x2e, IT8720F_SP1)
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#define GPIO_DEV PNP_DEV(0x2e, IT8720F_GPIO)
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static void mb_lpc_setup(void)
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void mb_lpc_setup(void)
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{
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/* Set up GPIOs on Super I/O. */
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ite_reg_write(GPIO_DEV, 0x25, 0x01);
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RCBA16(D29IR) = 0x0237;
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RCBA32(FD) |= FD_INTLAN;
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}
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void mainboard_romstage_entry(void)
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{
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// ch0 ch1
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#if CONFIG(BOARD_FOXCONN_G41S_K)
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const u8 spd_addrmap[4] = { 0x50, 0, 0, 0 };
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#else
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/* TODO adapt raminit such that other slots can be used
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* for single rank dimms */
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const u8 spd_addrmap[4] = { 0x50, 0, 0x52, 0 };
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#endif
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u8 boot_path = 0;
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u8 s3_resume;
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/* Set up southbridge and Super I/O GPIOs. */
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i82801gx_lpc_setup();
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mb_lpc_setup();
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ite_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
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console_init();
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enable_smbus();
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i82801gx_early_init();
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x4x_early_init();
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s3_resume = southbridge_detect_s3_resume();
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if (s3_resume)
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boot_path = BOOT_PATH_RESUME;
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if (MCHBAR32(PMSTS_MCHBAR) & PMSTS_WARM_RESET)
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boot_path = BOOT_PATH_WARM_RESET;
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sdram_initialize(boot_path, spd_addrmap);
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x4x_late_init(s3_resume);
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printk(BIOS_DEBUG, "x4x late init complete\n");
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}
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void mb_get_spd_map(u8 spd_map[4])
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{
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spd_map[0] = 0x50;
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if (CONFIG(BOARD_FOXCONN_G41M))
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spd_map[2] = 0x52;
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}
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* GNU General Public License for more details.
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*/
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#include <stdint.h>
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#include <device/pci_def.h>
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#include <device/pci_ops.h>
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#include <console/console.h>
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#include <southbridge/intel/i82801gx/i82801gx.h>
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#include <southbridge/intel/common/pmclib.h>
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#include <northbridge/intel/x4x/x4x.h>
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#include <arch/romstage.h>
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#include <superio/ite/it8718f/it8718f.h>
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#include <superio/ite/common/ite.h>
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* We should use standard gpio.h eventually
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*/
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static void mb_lpc_init(void)
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void mb_lpc_setup(void)
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{
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pci_devfn_t dev;
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ite_reg_write(EC_DEV, 0x70, 0x00); // Don't use IRQ9
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ite_reg_write(EC_DEV, 0x30, 0x01); // Enable
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ite_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
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/* Disable SIO reboot */
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ite_reg_write(GPIO_DEV, 0xEF, 0x7E);
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/* IRQ routing */
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RCBA32(D31IP) = 0x00002210;
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RCBA32(D30IP) = 0x00002100;
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RCBA32(D27IR) = 0x00000000;
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}
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void mainboard_romstage_entry(void)
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void mb_get_spd_map(u8 spd_map[4])
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{
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// ch0 ch1
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const u8 spd_addrmap[4] = { 0x50, 0, 0x52, 0 };
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u8 boot_path = 0;
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u8 s3_resume;
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/* Set southbridge and Super I/O GPIOs. */
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i82801gx_lpc_setup();
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mb_lpc_init();
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ite_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
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/* Disable SIO reboot */
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ite_reg_write(GPIO_DEV, 0xEF, 0x7E);
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console_init();
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enable_smbus();
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i82801gx_early_init();
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x4x_early_init();
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s3_resume = southbridge_detect_s3_resume();
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if (s3_resume)
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boot_path = BOOT_PATH_RESUME;
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if (MCHBAR32(PMSTS_MCHBAR) & PMSTS_WARM_RESET)
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boot_path = BOOT_PATH_WARM_RESET;
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sdram_initialize(boot_path, spd_addrmap);
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x4x_late_init(s3_resume);
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|
||||
printk(BIOS_DEBUG, "x4x late init complete\n");
|
||||
|
||||
spd_map[0] = 0x50;
|
||||
spd_map[2] = 0x52;
|
||||
}
|
||||
|
|
|
@ -16,19 +16,14 @@
|
|||
*/
|
||||
|
||||
#include <device/pnp_ops.h>
|
||||
#include <device/pci_ops.h>
|
||||
#include <console/console.h>
|
||||
#include <arch/romstage.h>
|
||||
#include <northbridge/intel/x4x/x4x.h>
|
||||
#include <southbridge/intel/common/pmclib.h>
|
||||
#include <southbridge/intel/i82801gx/i82801gx.h>
|
||||
#include <superio/winbond/common/winbond.h>
|
||||
#include <superio/winbond/w83627dhg/w83627dhg.h>
|
||||
|
||||
#define SERIAL_DEV PNP_DEV(0x2e, W83627DHG_SP1)
|
||||
#define LPC_DEV PCI_DEV(0, 0x1f, 0)
|
||||
|
||||
static void mb_lpc_setup(void)
|
||||
void mb_lpc_setup(void)
|
||||
{
|
||||
/* Set GPIOs on superio, enable UART */
|
||||
pnp_enter_ext_func_mode(SERIAL_DEV);
|
||||
|
@ -38,40 +33,15 @@ static void mb_lpc_setup(void)
|
|||
|
||||
pnp_exit_ext_func_mode(SERIAL_DEV);
|
||||
|
||||
winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
|
||||
|
||||
/* IRQ routing */
|
||||
RCBA16(D31IR) = 0x0132;
|
||||
RCBA16(D29IR) = 0x0237;
|
||||
}
|
||||
|
||||
void mainboard_romstage_entry(void)
|
||||
void mb_get_spd_map(u8 spd_map[4])
|
||||
{
|
||||
// ch0 ch1
|
||||
const u8 spd_addrmap[4] = { 0x50, 0, 0x52, 0 };
|
||||
u8 boot_path = 0;
|
||||
u8 s3_resume;
|
||||
|
||||
/* Set southbridge and Super I/O GPIOs. */
|
||||
i82801gx_lpc_setup();
|
||||
mb_lpc_setup();
|
||||
winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
|
||||
|
||||
console_init();
|
||||
|
||||
enable_smbus();
|
||||
|
||||
i82801gx_early_init();
|
||||
x4x_early_init();
|
||||
|
||||
s3_resume = southbridge_detect_s3_resume();
|
||||
if (s3_resume)
|
||||
boot_path = BOOT_PATH_RESUME;
|
||||
if (MCHBAR32(PMSTS_MCHBAR) & PMSTS_WARM_RESET)
|
||||
boot_path = BOOT_PATH_WARM_RESET;
|
||||
|
||||
sdram_initialize(boot_path, spd_addrmap);
|
||||
|
||||
x4x_late_init(s3_resume);
|
||||
|
||||
printk(BIOS_DEBUG, "x4x late init complete\n");
|
||||
|
||||
spd_map[0] = 0x50;
|
||||
spd_map[2] = 0x52;
|
||||
}
|
||||
|
|
|
@ -14,23 +14,14 @@
|
|||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#include <device/pci_ops.h>
|
||||
#include <console/console.h>
|
||||
#include <southbridge/intel/i82801jx/i82801jx.h>
|
||||
#include <southbridge/intel/common/pmclib.h>
|
||||
#include <northbridge/intel/x4x/x4x.h>
|
||||
#include <arch/romstage.h>
|
||||
#include <superio/winbond/w83627dhg/w83627dhg.h>
|
||||
#include <superio/winbond/common/winbond.h>
|
||||
|
||||
#define SERIAL_DEV PNP_DEV(0x2e, W83627DHG_SP1)
|
||||
#define LPC_DEV PCI_DEV(0, 0x1f, 0)
|
||||
|
||||
/* Early mainboard specific GPIO setup.
|
||||
* We should use standard gpio.h eventually
|
||||
*/
|
||||
|
||||
static void mb_misc_rcba(void)
|
||||
void mb_lpc_setup(void)
|
||||
{
|
||||
RCBA32(0x3410) = 0x00060464;
|
||||
RCBA32(RCBA_BUC) &= ~BUC_LAND;
|
||||
|
@ -38,35 +29,14 @@ static void mb_misc_rcba(void)
|
|||
RCBA32(0x341c) = 0xbf7f001f;
|
||||
RCBA32(0x3430) = 0x00000002;
|
||||
RCBA32(0x3f00) = 0x0000000b;
|
||||
}
|
||||
|
||||
void mainboard_romstage_entry(void)
|
||||
{
|
||||
const u8 spd_addrmap[4] = { 0x50, 0x51, 0x52, 0x53 };
|
||||
u8 boot_path = 0;
|
||||
u8 s3_resume;
|
||||
|
||||
/* Set southbridge and Super I/O GPIOs. */
|
||||
i82801jx_lpc_setup();
|
||||
mb_misc_rcba();
|
||||
winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
|
||||
|
||||
console_init();
|
||||
|
||||
enable_smbus();
|
||||
|
||||
i82801jx_early_init();
|
||||
x4x_early_init();
|
||||
|
||||
s3_resume = southbridge_detect_s3_resume();
|
||||
if (s3_resume)
|
||||
boot_path = BOOT_PATH_RESUME;
|
||||
if (MCHBAR32(PMSTS_MCHBAR) & PMSTS_WARM_RESET)
|
||||
boot_path = BOOT_PATH_WARM_RESET;
|
||||
|
||||
sdram_initialize(boot_path, spd_addrmap);
|
||||
|
||||
x4x_late_init(s3_resume);
|
||||
|
||||
printk(BIOS_DEBUG, "x4x late init complete\n");
|
||||
}
|
||||
|
||||
void mb_get_spd_map(u8 spd_map[4])
|
||||
{
|
||||
spd_map[0] = 0x50;
|
||||
spd_map[1] = 0x51;
|
||||
spd_map[2] = 0x52;
|
||||
spd_map[3] = 0x53;
|
||||
}
|
||||
|
|
|
@ -15,45 +15,18 @@
|
|||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#include <console/console.h>
|
||||
#include <southbridge/intel/i82801gx/i82801gx.h>
|
||||
#include <southbridge/intel/common/pmclib.h>
|
||||
#include <northbridge/intel/x4x/x4x.h>
|
||||
#include <arch/romstage.h>
|
||||
#include <device/pci_ops.h>
|
||||
#include <superio/smsc/smscsuperio/smscsuperio.h>
|
||||
|
||||
#define SERIAL_DEV PNP_DEV(0x2e, SMSCSUPERIO_SP1)
|
||||
#define LPC_DEV PCI_DEV(0, 0x1f, 0)
|
||||
|
||||
void mainboard_romstage_entry(void)
|
||||
void mb_lpc_setup(void)
|
||||
{
|
||||
// ch0 ch1
|
||||
const u8 spd_addrmap[4] = { 0x50, 0, 0x52, 0 };
|
||||
u8 boot_path = 0;
|
||||
u8 s3_resume;
|
||||
|
||||
/* Set southbridge and Super I/O GPIOs. */
|
||||
i82801gx_lpc_setup();
|
||||
smscsuperio_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
|
||||
|
||||
console_init();
|
||||
|
||||
enable_smbus();
|
||||
|
||||
i82801gx_early_init();
|
||||
x4x_early_init();
|
||||
|
||||
s3_resume = southbridge_detect_s3_resume();
|
||||
if (s3_resume)
|
||||
boot_path = BOOT_PATH_RESUME;
|
||||
if (MCHBAR32(PMSTS_MCHBAR) & PMSTS_WARM_RESET)
|
||||
boot_path = BOOT_PATH_WARM_RESET;
|
||||
|
||||
sdram_initialize(boot_path, spd_addrmap);
|
||||
|
||||
x4x_late_init(s3_resume);
|
||||
|
||||
printk(BIOS_DEBUG, "x4x late init complete\n");
|
||||
|
||||
}
|
||||
|
||||
void mb_get_spd_map(u8 spd_map[4])
|
||||
{
|
||||
spd_map[0] = 0x50;
|
||||
spd_map[2] = 0x52;
|
||||
}
|
||||
|
|
|
@ -23,6 +23,7 @@ romstage-y += memmap.c
|
|||
romstage-y += rcven.c
|
||||
romstage-y += raminit_tables.c
|
||||
romstage-y += dq_dqs.c
|
||||
romstage-y += romstage.c
|
||||
|
||||
ramstage-y += acpi.c
|
||||
ramstage-y += memmap.c
|
||||
|
|
|
@ -0,0 +1,71 @@
|
|||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#include <device/pci_ops.h>
|
||||
#include <console/console.h>
|
||||
#include <southbridge/intel/common/pmclib.h>
|
||||
#include <northbridge/intel/x4x/x4x.h>
|
||||
#include <arch/romstage.h>
|
||||
|
||||
#if CONFIG(SOUTHBRIDGE_INTEL_I82801JX)
|
||||
#include <southbridge/intel/i82801jx/i82801jx.h>
|
||||
#elif CONFIG(SOUTHBRIDGE_INTEL_I82801GX)
|
||||
#include <southbridge/intel/i82801gx/i82801gx.h>
|
||||
#endif
|
||||
|
||||
__weak void mb_pre_raminit_setup(int s3_resume)
|
||||
{
|
||||
}
|
||||
|
||||
void mainboard_romstage_entry(void)
|
||||
{
|
||||
u8 spd_addr_map[4] = {};
|
||||
u8 boot_path = 0;
|
||||
u8 s3_resume;
|
||||
|
||||
#if CONFIG(SOUTHBRIDGE_INTEL_I82801JX)
|
||||
i82801jx_lpc_setup();
|
||||
#elif CONFIG(SOUTHBRIDGE_INTEL_I82801GX)
|
||||
i82801gx_lpc_setup();
|
||||
#endif
|
||||
|
||||
mb_lpc_setup();
|
||||
|
||||
console_init();
|
||||
|
||||
enable_smbus();
|
||||
|
||||
#if CONFIG(SOUTHBRIDGE_INTEL_I82801JX)
|
||||
i82801jx_early_init();
|
||||
#elif CONFIG(SOUTHBRIDGE_INTEL_I82801GX)
|
||||
i82801gx_early_init();
|
||||
#endif
|
||||
|
||||
x4x_early_init();
|
||||
|
||||
s3_resume = southbridge_detect_s3_resume();
|
||||
mb_pre_raminit_setup(s3_resume);
|
||||
|
||||
if (s3_resume)
|
||||
boot_path = BOOT_PATH_RESUME;
|
||||
if (MCHBAR32(PMSTS_MCHBAR) & PMSTS_WARM_RESET)
|
||||
boot_path = BOOT_PATH_WARM_RESET;
|
||||
|
||||
mb_get_spd_map(spd_addr_map);
|
||||
sdram_initialize(boot_path, spd_addr_map);
|
||||
|
||||
x4x_late_init(s3_resume);
|
||||
|
||||
printk(BIOS_DEBUG, "x4x late init complete\n");
|
||||
}
|
|
@ -373,6 +373,9 @@ enum ddr2_signals {
|
|||
|
||||
void x4x_early_init(void);
|
||||
void x4x_late_init(int s3resume);
|
||||
void mb_lpc_setup(void);
|
||||
void mb_get_spd_map(u8 spd_map[4]);
|
||||
void mb_pre_raminit_setup(int s3_resume);
|
||||
u32 decode_igd_memory_size(u32 gms);
|
||||
u32 decode_igd_gtt_size(u32 gsm);
|
||||
u32 decode_tseg_size(const u32 esmramc);
|
||||
|
|
Loading…
Reference in New Issue