AMD fam10: Drop PCI_BUS_SEGN_BITS
All boards in tree use 0. Looks like this is all work that was never completed and tested. We also have static setting sysconf.segbit=0 which would conflict with PCI_BUS_SEGN_BITS>0. Having PCI_BUS_SEGN_BITS>0 would also require PCI MMCONF support to cover over 255 buses. Change-Id: I060efc44d1560541473b01690c2e8192863c1eb5 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/8554 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
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@ -267,7 +267,7 @@ static inline pci_devfn_t pci_io_locate_device(unsigned pci_id, pci_devfn_t dev)
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static inline pci_devfn_t pci_locate_device(unsigned pci_id, pci_devfn_t dev)
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static inline pci_devfn_t pci_locate_device(unsigned pci_id, pci_devfn_t dev)
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{
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{
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for(; dev <= PCI_DEV(255|(((1<<CONFIG_PCI_BUS_SEGN_BITS)-1)<<8), 31, 7); dev += PCI_DEV(0,0,1)) {
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for(; dev <= PCI_DEV(255, 31, 7); dev += PCI_DEV(0,0,1)) {
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unsigned int id;
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unsigned int id;
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id = pci_read_config32(dev, 0);
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id = pci_read_config32(dev, 0);
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if (id == pci_id) {
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if (id == pci_id) {
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@ -259,10 +259,6 @@ config PCIEXP_CLK_PM
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help
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help
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Detect and enable Clock Power Management on PCIe.
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Detect and enable Clock Power Management on PCIe.
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config PCI_BUS_SEGN_BITS
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int
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default 0
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config EARLY_PCI_BRIDGE
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config EARLY_PCI_BRIDGE
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bool "Early PCI bridge"
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bool "Early PCI bridge"
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depends on PCI
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depends on PCI
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@ -251,20 +251,11 @@ const char *dev_path(device_t dev)
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memcpy(buffer, "Root Device", 12);
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memcpy(buffer, "Root Device", 12);
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break;
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break;
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case DEVICE_PATH_PCI:
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case DEVICE_PATH_PCI:
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#if CONFIG_PCI_BUS_SEGN_BITS
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snprintf(buffer, sizeof (buffer),
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"PCI: %04x:%02x:%02x.%01x",
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dev->bus->secondary >> 8,
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dev->bus->secondary & 0xff,
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PCI_SLOT(dev->path.pci.devfn),
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PCI_FUNC(dev->path.pci.devfn));
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#else
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snprintf(buffer, sizeof (buffer),
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snprintf(buffer, sizeof (buffer),
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"PCI: %02x:%02x.%01x",
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"PCI: %02x:%02x.%01x",
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dev->bus->secondary,
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dev->bus->secondary,
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PCI_SLOT(dev->path.pci.devfn),
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PCI_SLOT(dev->path.pci.devfn),
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PCI_FUNC(dev->path.pci.devfn));
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PCI_FUNC(dev->path.pci.devfn));
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#endif
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break;
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break;
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case DEVICE_PATH_PNP:
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case DEVICE_PATH_PNP:
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snprintf(buffer, sizeof (buffer), "PNP: %04x.%01x",
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snprintf(buffer, sizeof (buffer), "PNP: %04x.%01x",
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@ -643,14 +634,8 @@ void report_resource_stored(device_t dev, struct resource *resource,
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buf[0] = '\0';
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buf[0] = '\0';
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if (resource->flags & IORESOURCE_PCI_BRIDGE) {
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if (resource->flags & IORESOURCE_PCI_BRIDGE) {
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#if CONFIG_PCI_BUS_SEGN_BITS
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snprintf(buf, sizeof (buf),
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"bus %04x:%02x ", dev->bus->secondary >> 8,
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dev->link_list->secondary & 0xff);
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#else
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snprintf(buf, sizeof (buf),
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snprintf(buf, sizeof (buf),
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"bus %02x ", dev->link_list->secondary);
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"bus %02x ", dev->link_list->secondary);
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#endif
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}
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}
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printk(BIOS_DEBUG, "%s %02lx <- [0x%010llx - 0x%010llx] size 0x%08llx "
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printk(BIOS_DEBUG, "%s %02lx <- [0x%010llx - 0x%010llx] size 0x%08llx "
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"gran 0x%02x %s%s%s\n", dev_path(dev), resource->index,
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"gran 0x%02x %s%s%s\n", dev_path(dev), resource->index,
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@ -855,19 +840,6 @@ void show_one_resource(int debug_level, struct device *dev,
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end = resource_end(resource);
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end = resource_end(resource);
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buf[0] = '\0';
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buf[0] = '\0';
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/*
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if (resource->flags & IORESOURCE_BRIDGE) {
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#if CONFIG_PCI_BUS_SEGN_BITS
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snprintf(buf, sizeof (buf), "bus %04x:%02x ",
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dev->bus->secondary >> 8,
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dev->link[0].secondary & 0xff);
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#else
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snprintf(buf, sizeof (buf),
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"bus %02x ", dev->link[0].secondary);
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#endif
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}
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*/
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do_printk(debug_level, "%s %02lx <- [0x%010llx - 0x%010llx] "
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do_printk(debug_level, "%s %02lx <- [0x%010llx - 0x%010llx] "
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"size 0x%08llx gran 0x%02x %s%s%s\n", dev_path(dev),
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"size 0x%08llx gran 0x%02x %s%s%s\n", dev_path(dev),
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resource->index, base, end, resource->size, resource->gran,
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resource->index, base, end, resource->size, resource->gran,
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@ -1090,12 +1090,7 @@ unsigned int pci_scan_bus(struct bus *bus, unsigned min_devfn,
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struct device *old_devices;
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struct device *old_devices;
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struct device *child;
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struct device *child;
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#if CONFIG_PCI_BUS_SEGN_BITS
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printk(BIOS_DEBUG, "PCI: pci_scan_bus for bus %04x:%02x\n",
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bus->secondary >> 8, bus->secondary & 0xff);
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#else
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printk(BIOS_DEBUG, "PCI: pci_scan_bus for bus %02x\n", bus->secondary);
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printk(BIOS_DEBUG, "PCI: pci_scan_bus for bus %02x\n", bus->secondary);
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#endif
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/* Maximum sane devfn is 0xFF. */
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/* Maximum sane devfn is 0xFF. */
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if (max_devfn > 0xff) {
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if (max_devfn > 0xff) {
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@ -33,11 +33,7 @@ static inline void print_debug_addr(const char *str, void *val)
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static void print_debug_pci_dev(u32 dev)
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static void print_debug_pci_dev(u32 dev)
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{
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{
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#if !CONFIG_PCI_BUS_SEGN_BITS
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printk(BIOS_DEBUG, "PCI: %02x:%02x.%02x", (dev>>20) & 0xff, (dev>>15) & 0x1f, (dev>>12) & 0x7);
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printk(BIOS_DEBUG, "PCI: %02x:%02x.%02x", (dev>>20) & 0xff, (dev>>15) & 0x1f, (dev>>12) & 0x7);
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#else
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printk(BIOS_DEBUG, "PCI: %04x:%02x:%02x.%02x", (dev>>28) & 0x0f, (dev>>20) & 0xff, (dev>>15) & 0x1f, (dev>>12) & 0x7);
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#endif
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}
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}
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static inline void print_pci_devices(void)
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static inline void print_pci_devices(void)
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@ -76,27 +76,6 @@ void clear_config_map_reg(u32 nodeid, u32 linkn, u32 ht_c_index,
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}
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}
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}
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}
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#if CONFIG_PCI_BUS_SEGN_BITS
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u32 check_segn(device_t dev, u32 segbusn, u32 nodes,
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sys_info_conf_t *sysinfo)
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{
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//check segbusn here, We need every node have the same segn
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if ((segbusn & 0xff)>(0xe0-1)) {// use next segn
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u32 segn = (segbusn >> 8) & 0x0f;
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segn++;
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segbusn = segn<<8;
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}
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if (segbusn>>8) {
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u32 val;
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val = pci_read_config32(dev, 0x160);
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val &= ~(0xf<<25);
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val |= (segbusn & 0xf00)<<(25-8);
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pci_write_config32(dev, 0x160, val);
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}
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return segbusn;
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}
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#endif
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u32 get_ht_c_index(u32 nodeid, u32 linkn, sys_info_conf_t *sysinfo)
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u32 get_ht_c_index(u32 nodeid, u32 linkn, sys_info_conf_t *sysinfo)
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{
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{
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@ -34,8 +34,6 @@ void set_config_map_reg(u32 nodeid, u32 linkn, u32 ht_c_index,
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u32 nodes);
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u32 nodes);
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void clear_config_map_reg(u32 nodeid, u32 linkn, u32 ht_c_index,
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void clear_config_map_reg(u32 nodeid, u32 linkn, u32 ht_c_index,
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u32 busn_min, u32 busn_max, u32 nodes);
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u32 busn_min, u32 busn_max, u32 nodes);
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u32 check_segn(device_t dev, u32 segbusn, u32 nodes,
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sys_info_conf_t *sysinfo);
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void store_ht_c_conf_bus(u32 nodeid, u32 linkn, u32 ht_c_index,
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void store_ht_c_conf_bus(u32 nodeid, u32 linkn, u32 ht_c_index,
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u32 busn_min, u32 busn_max,
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u32 busn_min, u32 busn_max,
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@ -167,7 +167,6 @@ static u32 amdfam10_scan_chain(device_t dev, u32 nodeid, struct bus *link, bool
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u32 max_bus;
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u32 max_bus;
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u32 min_bus;
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u32 min_bus;
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u32 busses;
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u32 busses;
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u32 segn = max>>8;
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#if CONFIG_SB_HT_CHAIN_ON_BUS0 > 1
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#if CONFIG_SB_HT_CHAIN_ON_BUS0 > 1
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u32 busn = max&0xff;
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u32 busn = max&0xff;
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#endif
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#endif
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@ -211,7 +210,7 @@ static u32 amdfam10_scan_chain(device_t dev, u32 nodeid, struct bus *link, bool
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else {
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else {
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min_bus = ((busn>>3) + 1) << 3; // one node can have 8 link and segn is the same
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min_bus = ((busn>>3) + 1) << 3; // one node can have 8 link and segn is the same
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}
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}
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max = min_bus | (segn<<8);
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max = min_bus;
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#else
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#else
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//other ...
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//other ...
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else {
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else {
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@ -221,7 +220,7 @@ static u32 amdfam10_scan_chain(device_t dev, u32 nodeid, struct bus *link, bool
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#else
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#else
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min_bus = ++max;
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min_bus = ++max;
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#endif
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#endif
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max_bus = 0xfc | (segn<<8);
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max_bus = 0xfc;
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link->secondary = min_bus;
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link->secondary = min_bus;
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link->subordinate = max_bus;
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link->subordinate = max_bus;
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@ -299,10 +298,6 @@ static unsigned amdfam10_scan_chains(device_t dev, unsigned max)
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max = amdfam10_scan_chain(dev, nodeid, link, is_sblink, max);
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max = amdfam10_scan_chain(dev, nodeid, link, is_sblink, max);
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}
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}
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#if CONFIG_PCI_BUS_SEGN_BITS
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max = check_segn(dev, max, sysconf.nodes, &sysconf);
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#endif
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for (link = dev->link_list; link; link = link->next) {
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for (link = dev->link_list; link; link = link->next) {
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bool is_sblink = (nodeid == 0) && (link->link_num == sblink);
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bool is_sblink = (nodeid == 0) && (link->link_num == sblink);
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if ((CONFIG_SB_HT_CHAIN_ON_BUS0 > 0) && is_sblink)
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if ((CONFIG_SB_HT_CHAIN_ON_BUS0 > 0) && is_sblink)
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