sb/intel/sandybridge/early_pch: Make DMI init more readable
Add a few comments and use known register values. Based on the "2nd Generation Intel® Core™ Processor Family Mobile" datasheet and the existing serialice trace. Tested on Lenovo T520 (Intel Sandy Bridge). Still boots to GNU/Linux. Change-Id: I404515b77a22324f55581f117d79630be4ba64dd Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32071 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Patrick Rudolph
Patrick Georgi
parent
25b35d317e
commit
bf7435087e
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@ -175,12 +175,23 @@ enum platform_type {
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#define DMIPVCCCTL 0x00c /* 16bit */
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#define DMIVC0RCAP 0x010 /* 32bit */
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#define DMIVC0RCTL0 0x014 /* 32bit */
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#define DMIVC0RCTL 0x014 /* 32bit */
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#define DMIVC0RSTS 0x01a /* 16bit */
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#define VC0NP 0x2
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#define DMIVC1RCAP 0x01c /* 32bit */
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#define DMIVC1RCTL 0x020 /* 32bit */
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#define DMIVC1RSTS 0x026 /* 16bit */
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#define VC1NP 0x2
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#define DMIVCPRCTL 0x02c /* 32bit */
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#define DMIVCPRSTS 0x032 /* 16bit */
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#define VCPNP 0x2
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#define DMIVCMRCTL 0x0038 /* 32 bit */
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#define DMIVCMRSTS 0x003e /* 16 bit */
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#define VCMNP 0x2
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#define DMILE1D 0x050 /* 32bit */
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#define DMILE1A 0x058 /* 64bit */
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@ -190,7 +201,7 @@ enum platform_type {
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#define DMILCAP 0x084 /* 32bit */
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#define DMILCTL 0x088 /* 16bit */
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#define DMILSTS 0x08a /* 16bit */
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#define TXTRN (1 << 11)
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#define DMICTL1 0x0f0 /* 32bit */
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#define DMICTL2 0x0fc /* 32bit */
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@ -20,6 +20,7 @@
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#include <device/pci_def.h>
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#include <southbridge/intel/common/gpio.h>
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#include <southbridge/intel/common/pmbase.h>
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#include <console/console.h>
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/* For DMI bar. */
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#include <northbridge/intel/sandybridge/sandybridge.h>
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@ -68,36 +69,29 @@ write_iobp(u32 address, u32 val)
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read8(DEFAULT_RCBA + IOBPS); // call wait_iobp() instead here?
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}
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static void
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init_dmi (void)
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{
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volatile u32 tmp;
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int i;
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write32 (DEFAULT_DMIBAR + 0x0914,
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read32 (DEFAULT_DMIBAR + 0x0914) | 0x80000000);
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write32 (DEFAULT_DMIBAR + 0x0934,
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read32 (DEFAULT_DMIBAR + 0x0934) | 0x80000000);
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for (i = 0; i < 4; i++)
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{
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write32 (DEFAULT_DMIBAR + 0x0a00 + (i << 4),
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read32 (DEFAULT_DMIBAR + 0x0a00 + (i << 4)) & 0xf3ffffff);
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write32 (DEFAULT_DMIBAR + 0x0a04 + (i << 4),
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read32 (DEFAULT_DMIBAR + 0x0a04 + (i << 4)) | 0x800);
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DMIBAR32(0x0914) |= 0x80000000;
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DMIBAR32(0x0934) |= 0x80000000;
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for (i = 0; i < 4; i++) {
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DMIBAR32(0x0a00 + (i << 4)) &= 0xf3ffffff;
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DMIBAR32(0x0a04 + (i << 4)) |= 0x800;
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}
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write32 (DEFAULT_DMIBAR + 0x0c30, (read32 (DEFAULT_DMIBAR + 0x0c30)
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& 0xfffffff) | 0x40000000);
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for (i = 0; i < 2; i++)
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{
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write32 (DEFAULT_DMIBAR + 0x0904 + (i << 5),
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read32 (DEFAULT_DMIBAR + 0x0904 + (i << 5)) & 0xfe3fffff);
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write32 (DEFAULT_DMIBAR + 0x090c + (i << 5),
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read32 (DEFAULT_DMIBAR + 0x090c + (i << 5)) & 0xfff1ffff);
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DMIBAR32(0x0c30) = (DMIBAR32(0x0c30) & 0xfffffff) | 0x40000000;
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for (i = 0; i < 2; i++) {
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DMIBAR32(0x0904 + (i << 5)) &= 0xfe3fffff;
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DMIBAR32(0x090c + (i << 5)) &= 0xfff1ffff;
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}
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write32 (DEFAULT_DMIBAR + 0x090c,
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read32 (DEFAULT_DMIBAR + 0x090c) & 0xfe1fffff);
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write32 (DEFAULT_DMIBAR + 0x092c,
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read32 (DEFAULT_DMIBAR + 0x092c) & 0xfe1fffff);
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DMIBAR32(0x090c) &= 0xfe1fffff;
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DMIBAR32(0x092c) &= 0xfe1fffff;
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read32 (DEFAULT_DMIBAR + 0x0904); // !!! = 0x7a1842ec
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write32 (DEFAULT_DMIBAR + 0x0904, 0x7a1842ec);
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read32 (DEFAULT_DMIBAR + 0x090c); // !!! = 0x00000208
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@ -226,33 +220,54 @@ init_dmi (void)
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write32 (DEFAULT_DMIBAR + 0x0934, 0x98200280);
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read32 (DEFAULT_DMIBAR + 0x022c); // !!! = 0x00c26460
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write32 (DEFAULT_DMIBAR + 0x022c, 0x00c2403c);
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read8 (DEFAULT_RCBA + 0x21a4); // !!! = 0x42
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read32 (DEFAULT_RCBA + 0x21a4); // !!! = 0x00012c42
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read32 (DEFAULT_RCBA + 0x2340); // !!! = 0x0013001b
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write32 (DEFAULT_RCBA + 0x2340, 0x003a001b);
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read8 (DEFAULT_RCBA + 0x21b0); // !!! = 0x01
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write8 (DEFAULT_RCBA + 0x21b0, 0x02);
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read32 (DEFAULT_DMIBAR + 0x0084); // !!! = 0x0041ac41
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write32 (DEFAULT_DMIBAR + 0x0084, 0x0041ac42);
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read8 (DEFAULT_DMIBAR + 0x0088); // !!! = 0x00
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write8 (DEFAULT_DMIBAR + 0x0088, 0x20);
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read16 (DEFAULT_DMIBAR + 0x008a); // !!! = 0x0041
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read8 (DEFAULT_DMIBAR + 0x0088); // !!! = 0x00
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write8 (DEFAULT_DMIBAR + 0x0088, 0x20);
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read16 (DEFAULT_DMIBAR + 0x008a); // !!! = 0x0042
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read16 (DEFAULT_DMIBAR + 0x008a); // !!! = 0x0042
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/* Link Capabilities Register */
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RCBA32(0x21a4) = (RCBA32(0x21a4) & ~0x3fc00) |
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(3 << 10) | // L0s and L1 entry supported
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(2 << 12) | // L0s 128 ns to less than 256 ns
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(2 << 15); // L1 2 us to less than 4 us
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read32 (DEFAULT_DMIBAR + 0x0014); // !!! = 0x8000007f
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write32 (DEFAULT_DMIBAR + 0x0014, 0x80000019);
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read32 (DEFAULT_DMIBAR + 0x0020); // !!! = 0x01000000
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write32 (DEFAULT_DMIBAR + 0x0020, 0x81000022);
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read32 (DEFAULT_DMIBAR + 0x002c); // !!! = 0x02000000
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write32 (DEFAULT_DMIBAR + 0x002c, 0x82000044);
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read32 (DEFAULT_DMIBAR + 0x0038); // !!! = 0x07000080
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write32 (DEFAULT_DMIBAR + 0x0038, 0x87000080);
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read8 (DEFAULT_DMIBAR + 0x0004); // !!! = 0x00
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write8 (DEFAULT_DMIBAR + 0x0004, 0x01);
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RCBA32(0x2340) = (RCBA32(0x2340) & ~0xff0000) | (0x3a << 16);
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RCBA8(0x21b0) = (RCBA8(0x21b0) & ~0xf) | 2;
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/* Write once settings. */
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DMIBAR32(DMILCAP) = (DMIBAR32(DMILCAP) & ~0x3f00f) |
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(2 << 0) | // 5GT/s
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(2 << 12) | // L0s 128 ns to less than 256 ns
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(2 << 15); // L1 2 us to less than 4 us
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DMIBAR8(DMILCTL) |= 0x20; // Retrain link
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while (DMIBAR16(DMILSTS) & TXTRN)
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;
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DMIBAR8(DMILCTL) |= 0x20; // Retrain link
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while (DMIBAR16(DMILSTS) & TXTRN)
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;
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const u8 w = (DMIBAR16(DMILSTS) >> 4) & 0x1f;
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const u16 t = (DMIBAR16(DMILSTS) & 0xf) * 2500;
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printk(BIOS_DEBUG, "DMI: Running at X%x @ %dMT/s\n", w, t);
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/*
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* Virtual Channel resources must match settings in RCBA!
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*
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* Channel Vp and Vm are documented in
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* "Desktop 4th Generation Intel Core Processor Family, Desktop Intel
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* Pentium Processor Family, and Desktop Intel Celeron Processor Family
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* Vol. 2"
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*/
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/* Channel 0: Enable, Set ID to 0, map TC0 and TC3 and TC4 to VC0. */
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DMIBAR32(DMIVC0RCTL) = (1 << 31) | (0 << 24) | (0x0c << 1) | 1;
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/* Channel 1: Enable, Set ID to 1, map TC1 and TC5 to VC1. */
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DMIBAR32(DMIVC1RCTL) = (1 << 31) | (1 << 24) | (0x11 << 1);
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/* Channel p: Enable, Set ID to 2, map TC2 and TC6 to VCp */
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DMIBAR32(DMIVCPRCTL) = (1 << 31) | (2 << 24) | (0x22 << 1);
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/* Channel m: Enable, Set ID to 0, map TC7 to VCm */
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DMIBAR32(DMIVCMRCTL) = (1 << 31) | (7 << 24) | (0x40 << 1);
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/* Set Extended VC Count (EVCC) to 1 as Channel 1 is active. */
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DMIBAR8(DMIPVCCAP1) |= 1;
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read32 (DEFAULT_RCBA + 0x0050); // !!! = 0x01200654
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write32 (DEFAULT_RCBA + 0x0050, 0x01200654);
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@ -261,27 +276,76 @@ init_dmi (void)
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read32 (DEFAULT_RCBA + 0x0050); // !!! = 0x012a0654
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read8 (DEFAULT_RCBA + 0x1114); // !!! = 0x00
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write8 (DEFAULT_RCBA + 0x1114, 0x05);
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read32 (DEFAULT_RCBA + 0x2014); // !!! = 0x80000011
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write32 (DEFAULT_RCBA + 0x2014, 0x80000019);
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read32 (DEFAULT_RCBA + 0x2020); // !!! = 0x00000000
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write32 (DEFAULT_RCBA + 0x2020, 0x81000022);
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read32 (DEFAULT_RCBA + 0x2020); // !!! = 0x81000022
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read32 (DEFAULT_RCBA + 0x2030); // !!! = 0x00000000
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write32 (DEFAULT_RCBA + 0x2030, 0x82000044);
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read32 (DEFAULT_RCBA + 0x2030); // !!! = 0x82000044
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read32 (DEFAULT_RCBA + 0x2040); // !!! = 0x00000000
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write32 (DEFAULT_RCBA + 0x2040, 0x87000080);
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read32 (DEFAULT_RCBA + 0x0050); // !!! = 0x012a0654
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write32 (DEFAULT_RCBA + 0x0050, 0x812a0654);
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read32 (DEFAULT_RCBA + 0x0050); // !!! = 0x812a0654
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read16 (DEFAULT_RCBA + 0x201a); // !!! = 0x0000
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read16 (DEFAULT_RCBA + 0x2026); // !!! = 0x0000
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read16 (DEFAULT_RCBA + 0x2036); // !!! = 0x0000
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read16 (DEFAULT_RCBA + 0x2046); // !!! = 0x0000
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read16 (DEFAULT_DMIBAR + 0x001a); // !!! = 0x0000
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read16 (DEFAULT_DMIBAR + 0x0026); // !!! = 0x0000
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read16 (DEFAULT_DMIBAR + 0x0032); // !!! = 0x0000
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read16 (DEFAULT_DMIBAR + 0x003e); // !!! = 0x0000
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/*
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* Virtual Channel resources must match settings in DMIBAR!
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*
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* Some of the following settings are taken from
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* "Intel Core i5-600, i3-500 Desktop Processor Series and Intel
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* Pentium Desktop Processor 6000 Series Vol. 2" datasheet and
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* serialice traces.
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*/
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/* Virtual Channel 0 Resource Control Register.
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* Enable channel.
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* Set Virtual Channel Identifier.
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* Map TC0 and TC3 and TC4 to VC0.
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*/
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RCBA32(0x2014) = (1 << 31) | (0 << 24) | (0x0c << 1) | 1;
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/* Virtual Channel 1 Resource Control Register.
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* Enable channel.
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* Set Virtual Channel Identifier.
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* Map TC1 and TC5 to VC1.
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*/
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RCBA32(0x2020) = (1 << 31) | (1 << 24) | (0x11 << 1);
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/* Read back register */
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tmp = RCBA32(0x2020);
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/* Virtual Channel private Resource Control Register.
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* Enable channel.
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* Set Virtual Channel Identifier.
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* Map TC2 and TC6 to VCp.
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*/
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RCBA32(0x2030) = (1 << 31) | (2 << 24) | (0x22 << 1);
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/* Read back register */
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tmp = RCBA32(0x2030);
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/* Virtual Channel ME Resource Control Register.
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* Enable channel.
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* Set Virtual Channel Identifier.
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* Map TC7 to VCm.
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*/
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RCBA32(0x2040) = (1 << 31) | (7 << 24) | (0x40 << 1);
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/* Lock Virtual Channel Resource control register. */
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RCBA32(0x0050) |= 0x80000000;
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/* Read back register */
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tmp = RCBA32(0x0050);
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/* Wait for virtual channels negotiation pending */
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while (RCBA16(0x201a) & VCNEGPND)
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;
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while (RCBA16(0x2026) & VCNEGPND)
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;
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while (RCBA16(0x2036) & VCNEGPND)
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;
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while (RCBA16(0x2046) & VCNEGPND)
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;
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/*
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* BIOS Requirement: Check if DMI VC Negotiation was successful.
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* Wait for virtual channels negotiation pending.
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*/
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while (DMIBAR16(DMIVC0RSTS) & VC0NP)
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;
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while (DMIBAR16(DMIVC1RSTS) & VC1NP)
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;
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while (DMIBAR16(DMIVCPRSTS) & VCPNP)
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;
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while (DMIBAR16(DMIVCMRSTS) & VCMNP)
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;
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}
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void
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@ -310,6 +310,8 @@ early_usb_init (const struct southbridge_usb_port *portmap);
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#define IOTR2 0x1e90 /* 64bit */
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#define IOTR3 0x1e98 /* 64bit */
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#define VCNEGPND 2
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#define TCTL 0x3000 /* 8bit */
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#define NOINT 0
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