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arch/riscv/payload: Remove old RISC-V CSR names 

LLVM/clang 17 removed support for CSR names that are no longer included
in the RISC-V ISA Manual Privileged Specification since version 1.12.

Related LLVM commit: https://reviews.llvm.org/D149278

Change-Id: I7c8f2a06a109333f95230bf0a3056c8d5c8a9132
Signed-off-by: Lennart Eichhorn <lennarteichhorn@googlemail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79364
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
This commit is contained in:
Lennart Eichhorn 2023-12-01 16:18:14 +01:00 committed by Felix Singer
parent e06ebcd530
commit bf7eba7add
1 changed files with 0 additions and 7 deletions
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7
src/arch/riscv/payload.c
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@ -39,13 +39,6 @@ void run_payload(struct prog *prog, void *fdt, int payload_mode)
status = INSERT_FIELD(status, MSTATUS_MPIE, 0);
switch (payload_mode) {
case RISCV_PAYLOAD_MODE_U:
status = INSERT_FIELD(status, MSTATUS_MPP, PRV_U);
/* Trap vector base address point to the payload */
write_csr(utvec, doit);
/* disable U-Mode interrupt */
write_csr(uie, 0);
break;
case RISCV_PAYLOAD_MODE_S:
status = INSERT_FIELD(status, MSTATUS_MPP, PRV_S);
/* Trap vector base address point to the payload */