From bf81c24e078c3eaea6cc2cd53e681579543c03a2 Mon Sep 17 00:00:00 2001
From: John Su <john_su@compal.corp-partner.google.com>
Date: Wed, 16 Feb 2022 14:59:07 +0800
Subject: [PATCH] mb/google/brya/variants/felwinter: Adjust I2Cs CLK to be
 around 400 kHz

Need to tune I2C bus 0/1/3/5 clock frequency under the 400kHz for
audio, TPM, touchscreen, and touchpad.

Audio CLK: 385 kHz
TPM CLK: 380.5 kHz
Touch Screen CLK: 373.3 kHz
Touch Pad CLK: 372.7 kHz

BUG=b:218577918
BRANCH=master
TEST=emerge-brya coreboot chromeos-bootimage
     measure by scope with felwinter.

Signed-off-by: John Su <john_su@compal.corp-partner.google.com>
Change-Id: I3e5cc10d6605f9cc41fa6b31da07a81364b72fe0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62009
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
---
 .../google/brya/variants/felwinter/overridetree.cb   | 12 ++++++++++++
 1 file changed, 12 insertions(+)

diff --git a/src/mainboard/google/brya/variants/felwinter/overridetree.cb b/src/mainboard/google/brya/variants/felwinter/overridetree.cb
index 1bde55c9b9..d1842764f3 100644
--- a/src/mainboard/google/brya/variants/felwinter/overridetree.cb
+++ b/src/mainboard/google/brya/variants/felwinter/overridetree.cb
@@ -58,16 +58,28 @@ chip soc/intel/alderlake
 	register "common_soc_config" = "{
 		.i2c[0] = {
 			.speed = I2C_SPEED_FAST,
+			.rise_time_ns = 550,
+			.fall_time_ns = 400,
+			.data_hold_time_ns = 50,
 		},
 		.i2c[1] = {
 			.early_init = 1,
 			.speed = I2C_SPEED_FAST,
+			.rise_time_ns = 550,
+			.fall_time_ns = 400,
+			.data_hold_time_ns = 50,
 		},
 		.i2c[3] = {
 			.speed = I2C_SPEED_FAST,
+			.rise_time_ns = 550,
+			.fall_time_ns = 400,
+			.data_hold_time_ns = 50,
 		},
 		.i2c[5] = {
 			.speed = I2C_SPEED_FAST,
+			.rise_time_ns = 550,
+			.fall_time_ns = 400,
+			.data_hold_time_ns = 50,
 		},
 	}"