cpu/amd/fam10h-15h: Add tsc_freq_mhz() function
The AMD Family 10h/15h processors use a TSC that increments at the P0 core frequency. Allow coreboot to query the TSC frequency. Change-Id: I73ead4fd4af18991452d59985b667a54689778cd Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: https://review.coreboot.org/12834 Tested-by: build bot (Jenkins) Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
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src/cpu/amd/family_10h-family_15h
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@ -3,6 +3,8 @@ ramstage-y += model_10xxx_init.c
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ramstage-y += processor_name.c
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ramstage-y += processor_name.c
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romstage-y += update_microcode.c
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romstage-y += update_microcode.c
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romstage-y += tsc_freq.c
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ramstage-y += tsc_freq.c
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romstage-y += ram_calc.c
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romstage-y += ram_calc.c
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ramstage-y += ram_calc.c
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ramstage-y += ram_calc.c
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ramstage-y += monotonic_timer.c
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ramstage-y += monotonic_timer.c
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@ -0,0 +1,37 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2016 Raptor Engineering
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <stdint.h>
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#include <cpu/x86/msr.h>
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#include <cpu/x86/tsc.h>
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unsigned long tsc_freq_mhz(void)
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{
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msr_t msr;
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uint8_t cpufid;
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uint8_t cpudid;
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/* On Family 10h/15h CPUs the TSC increments
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* at the P0 clock rate. Read the P0 clock
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* frequency from the P0 MSR and convert
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* to MHz. See also the Family 15h BKDG
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* Rev. 3.14 page 569.
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*/
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msr = rdmsr(0xc0010064);
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cpufid = (msr.lo & 0x3f);
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cpudid = (msr.lo & 0x1c0) >> 6;
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return (100 * (cpufid + 0x10)) / (0x01 << cpudid);
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}
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