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mainboard/jetway/nf81-t56n-lf: Fix GPP missing CLK on PCI bridge. 

The platform dependent mainboard.c was incorrectly disabling the
second clock signal feeding the GPP ports. This results in
spurious hangs by calling the set_pcie_dereset() SB CIMx callback
many times. This also stops coreboot from finding the second NIC
behind the pci 15.0 bridge.

Change-Id: I9f2370f6e05d1c5532fbca8203e32ab1ff15266a
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/5355
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
Reviewed-by: Idwer Vollering <vidwer@gmail.com>
This commit is contained in:
Edward O'Callaghan 2014-03-09 17:46:39 +11:00 committed by Idwer Vollering
parent 8340666cb1
commit bfa29dc021
1 changed files with 3 additions and 3 deletions
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6
src/mainboard/jetway/nf81-t56n-lf/mainboard.c
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@ -65,11 +65,11 @@ static void mainboard_enable(device_t dev)
acpi_slp_type = acpi_get_sleep_type(); acpi_slp_type = acpi_get_sleep_type();
#endif #endif
/* enable GPP CLK0 thru CLK1 */ /* enable GPP CLK0 thru CLK3 (interleaved) */
/* disable GPP CLK2 thru SLT_GFX_CLK */ /* disable GPP CLK4 thru SLT_GFX_CLK */
u8 *misc_mem_clk_cntrl = (u8 *)(ACPI_MMIO_BASE + MISC_BASE); u8 *misc_mem_clk_cntrl = (u8 *)(ACPI_MMIO_BASE + MISC_BASE);
*(misc_mem_clk_cntrl + 0) = 0xFF; *(misc_mem_clk_cntrl + 0) = 0xFF;
*(misc_mem_clk_cntrl + 1) = 0x00; *(misc_mem_clk_cntrl + 1) = 0xFF;
*(misc_mem_clk_cntrl + 2) = 0x00; *(misc_mem_clk_cntrl + 2) = 0x00;
*(misc_mem_clk_cntrl + 3) = 0x00; *(misc_mem_clk_cntrl + 3) = 0x00;
*(misc_mem_clk_cntrl + 4) = 0x00; *(misc_mem_clk_cntrl + 4) = 0x00;