mb/system76/tgl-u: Enable reporting CPU C10 state over eSPI

This allows the EC to detect C10 using eSPI instead of a dedicated pin.

Change-Id: I58c03d91466b869d53c9ee2cbbe50adc32539494
Signed-off-by: Jeremy Soller <jeremy@system76.com>
Signed-off-by: Tim Crawford <tcrawford@system76.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73689
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

src/mainboard/system76/tgl-u/variants/darp7/ramstage.c

@@ -12,4 +12,7 @@ void mainboard_silicon_init_params(FSP_S_CONFIG *params)
 	// IOM config
 	params->PchUsbOverCurrentEnable = 0;
 	params->PortResetMessageEnable[5] = 1; // J_TYPEC2
+
+	// Enable reporting CPU C10 state over eSPI
+	params->PchEspiHostC10ReportEnable = 1;
 }

src/mainboard/system76/tgl-u/variants/galp5/ramstage.c

@@ -12,4 +12,7 @@ void mainboard_silicon_init_params(FSP_S_CONFIG *params)
 	// IOM config
 	params->PchUsbOverCurrentEnable = 0;
 	params->PortResetMessageEnable[5] = 1; // J_TYPEC2
+
+	// Enable reporting CPU C10 state over eSPI
+	params->PchEspiHostC10ReportEnable = 1;
 }

src/mainboard/system76/tgl-u/variants/lemp10/ramstage.c

@@ -12,4 +12,7 @@ void mainboard_silicon_init_params(FSP_S_CONFIG *params)
 	// IOM config
 	params->PchUsbOverCurrentEnable = 0;
 	params->PortResetMessageEnable[2] = 1; // J_TYPEC1
+
+	// Enable reporting CPU C10 state over eSPI
+	params->PchEspiHostC10ReportEnable = 1;
 }