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mb/google/eve: Tune I2C4 hold times 

Tune PCH I2C4 hold times to ensure the frequency is always <400KHz.

BUG=b:67029862
TEST=boot on eve and measure I2C4 at Tp262 to be 385KHz

Change-Id: Ie93c5c40bc74069b285f6c3ee311f1bd7cefcaf1
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Change-Id: Iceabc806a17b9e6a144a4f6288c6cca790d03950
Original-Signed-off-by: Duncan Laurie <dlaurie@google.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/739841
Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/22448
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
This commit is contained in:
Duncan Laurie 2017-10-26 08:44:16 -07:00 committed by Duncan Laurie
parent ebd67c23ed
commit bfd17e3421
1 changed files with 6 additions and 2 deletions
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8
src/mainboard/google/eve/devicetree.cb
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@ -198,8 +198,12 @@ chip soc/intel/skylake
register "i2c_voltage[4]" = "I2C_VOLTAGE_1V8"
register "i2c[4]" = "{
.speed = I2C_SPEED_FAST,
.rise_time_ns = 240,
.fall_time_ns = 30,
.speed_config[0] = {
.speed = I2C_SPEED_FAST,
.scl_lcnt = 176,
.scl_hcnt = 95,
.sda_hold = 36,
}
}"
# Must leave UART0 enabled or SD/eMMC will not work as PCI