rockchip: support pwm regulator
BUG=None TEST=Boot Veyron Pinky and test the VDD_LOG Original-Change-Id: Ie2eef918e04ba0e13879e915b0b0bef44aef550e Original-Signed-off-by: huang lin <hl@rock-chips.com> Original-Reviewed-on: https://chromium-review.googlesource.com/219753 Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Original-Commit-Queue: Julius Werner <jwerner@chromium.org> Change-Id: I444b47564d90b3480b351fdd8460e5b94e71927c (cherry picked from commit 4491d9c4037161fd8c4cc40856167bf73182fda6) Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/9240 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins)
This commit is contained in:
huang lin
Aaron Durbin
parent
bbcffd9e25
commit
bfdd732b80
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@ -28,11 +28,32 @@
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#include <timestamp.h>
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#include <arch/cache.h>
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#include <arch/exception.h>
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#include <stdlib.h>
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#include <assert.h>
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#include <vendorcode/google/chromeos/chromeos.h>
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#include <soc/rockchip/rk3288/sdram.h>
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#include <soc/rockchip/rk3288/clock.h>
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#include <soc/rockchip/rk3288/pwm.h>
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#include <soc/rockchip/rk3288/grf.h>
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#include "timer.h"
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static void regulate_vdd_log(unsigned int mv)
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{
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unsigned int duty_ns;
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const u32 period_ns = 2000; /* pwm period: 2000ns */
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const u32 max_regulator_mv = 1350; /* 1.35V */
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const u32 min_regulator_mv = 870; /* 0.87V */
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writel(IOMUX_PWM1, &rk3288_grf->iomux_pwm1);
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assert((mv >= min_regulator_mv) && (mv <= max_regulator_mv));
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duty_ns = (max_regulator_mv - mv) * period_ns /
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(max_regulator_mv - min_regulator_mv);
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pwm_init(1, period_ns, duty_ns);
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}
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void main(void)
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{
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#if CONFIG_COLLECT_TIMESTAMPS
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@ -49,6 +70,8 @@ void main(void)
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console_init();
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/* vdd_log 1200mv is enough for ddr run 666Mhz */
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regulate_vdd_log(1200);
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#if CONFIG_COLLECT_TIMESTAMPS
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before_dram_time = timestamp_get();
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#endif
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@ -51,6 +51,7 @@ romstage-y += gpio.c
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romstage-y += spi.c
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romstage-y += media.c
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romstage-y += sdram.c
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romstage-y += pwm.c
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ramstage-y += soc.c
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ramstage-y += cbmem.c
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@ -62,6 +63,7 @@ ramstage-y += spi.c
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ramstage-y += gpio.c
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ramstage-y += media.c
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ramstage-y += rk808.c
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ramstage-y += pwm.c
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ramstage-$(CONFIG_DRIVERS_UART) += uart.c
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$(objcbfs)/bootblock.raw.elf: $(objcbfs)/bootblock.elf
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@ -109,6 +109,32 @@ static const struct pll_div cpll_init_cfg = PLL_DIVISORS(CPLL_HZ, 2, 4);
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/* m0 core axi clock div: clk = clk_src / (div_con + 1) */
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#define M0_DIV_MSK (0xF)
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/*******************CLKSEL1 BITS***************************/
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/* pd bus clk pll sel: codec or general */
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#define PD_BUS_SEL_PLL_MSK (1 << 15)
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#define PD_BUS_SEL_CPLL (0 << 15)
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#define PD_BUS_SEL_GPLL (1 << 15)
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/* pd bus pclk div:
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* pclk = pd_bus_aclk /(div + 1)
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*/
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#define PD_BUS_PCLK_DIV_SHIFT (12)
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#define PD_BUS_PCLK_DIV_MSK (0x7 << 12)
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/* pd bus hclk div:
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* aclk_bus: hclk_bus = 1:1 or 2:1 or 4:1
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*/
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#define PD_BUS_HCLK_DIV_SHIFT (8)
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#define PD_BUS_HCLK_DIV_MSK (0x3 << 8)
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/* pd bus aclk div:
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* pd_bus_aclk = pd_bus_src_clk /(div0 * div1)
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*/
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#define PD_BUS_ACLK_DIV0_SHIFT (3)
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#define PD_BUS_ACLK_DIV0_MASK (0x1f << 3)
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#define PD_BUS_ACLK_DIV1_SHIFT (0)
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#define PD_BUS_ACLK_DIV1_MASK (0x7 << 0)
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/*******************CLKSEL10 BITS***************************/
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/* peripheral bus clk pll sel: codec or general */
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#define PERI_SEL_PLL_MSK (1 << 15)
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@ -133,6 +159,7 @@ static const struct pll_div cpll_init_cfg = PLL_DIVISORS(CPLL_HZ, 2, 4);
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*/
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#define PERI_ACLK_DIV_SHIFT (0x0)
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#define PERI_ACLK_DIV_MSK (0x1F)
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#define PERI_ACLK_DIV_SHIFT (0)
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/*******************CLKSEL37 BITS***************************/
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#define L2_DIV_MSK (0x7)
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@ -186,8 +213,28 @@ static int rkclk_set_pll(u32 *pll_con, const struct pll_div *pll_div_cfg)
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return 0;
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}
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/*
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TODO:
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it should be replaced by lib.h function
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'unsigned long log2(unsigned long x)'
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*/
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static unsigned int log2(unsigned int value)
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{
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unsigned int div = 0;
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while (value != 1) {
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div++;
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value = ALIGN_UP(value, 2) / 2;
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}
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return div;
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}
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void rkclk_init(void)
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{
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u32 aclk_div;
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u32 hclk_div;
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u32 pclk_div;
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/* pll enter slow-mode */
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writel(RK_CLRSETBITS(APLL_MODE_MSK, APLL_MODE_SLOW)
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| RK_CLRSETBITS(GPLL_MODE_MSK, GPLL_MODE_SLOW)
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@ -231,16 +278,52 @@ void rkclk_init(void)
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| RK_CLRSETBITS(PCLK_DBG_DIV_MSK, (3 << PCLK_DBG_DIV_SHIFT)),
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&cru_ptr->cru_clksel_con[37]);
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/*
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* pd_bus clock pll source selection and
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* set up dependent divisors for PCLK/HCLK and ACLK clocks.
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*/
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aclk_div = GPLL_HZ / PD_BUS_ACLK_HZ - 1;
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assert((aclk_div + 1) * PD_BUS_ACLK_HZ == GPLL_HZ && aclk_div < 0x1f);
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hclk_div = PD_BUS_ACLK_HZ / PD_BUS_HCLK_HZ - 1;
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assert((hclk_div + 1) * PD_BUS_HCLK_HZ ==
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PD_BUS_ACLK_HZ && (hclk_div < 0x4) && (hclk_div != 0x2));
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pclk_div = PD_BUS_ACLK_HZ / PD_BUS_PCLK_HZ - 1;
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assert((pclk_div + 1) * PD_BUS_PCLK_HZ ==
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PD_BUS_ACLK_HZ && pclk_div < 0x7);
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writel(RK_SETBITS(PD_BUS_SEL_GPLL)
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| RK_CLRSETBITS(PD_BUS_PCLK_DIV_MSK,
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pclk_div << PD_BUS_PCLK_DIV_SHIFT)
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| RK_CLRSETBITS(PD_BUS_HCLK_DIV_MSK,
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hclk_div << PD_BUS_HCLK_DIV_SHIFT)
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| RK_CLRSETBITS(PD_BUS_ACLK_DIV0_MASK,
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aclk_div << PD_BUS_ACLK_DIV0_SHIFT)
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| RK_CLRSETBITS(PD_BUS_ACLK_DIV1_MASK, 0 << 0),
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&cru_ptr->cru_clksel_con[1]);
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/*
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* peri clock pll source selection and
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* set up dependent divisors for PCLK/HCLK and ACLK clocks.
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* peri clock select gpll, gpll clk = 594MHz
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* aclk = 148.5MHz, hclk = 148.5Mhz, pclk = 74.25MHz
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*/
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writel(RK_SETBITS(PERI_SEL_PLL_MSK)
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| RK_CLRSETBITS(PERI_PCLK_DIV_MSK, 1 << PERI_PCLK_DIV_SHIFT)
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| RK_CLRSETBITS(PERI_HCLK_DIV_MSK, 0 << PERI_HCLK_DIV_SHIFT)
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| RK_CLRSETBITS(PERI_ACLK_DIV_MSK, 3 << 0),
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aclk_div = GPLL_HZ / PERI_ACLK_HZ - 1;
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assert((aclk_div + 1) * PERI_ACLK_HZ == GPLL_HZ && aclk_div < 0x1f);
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hclk_div = log2(PERI_ACLK_HZ / PERI_HCLK_HZ);
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assert((1 << hclk_div) * PERI_HCLK_HZ ==
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PERI_ACLK_HZ && (hclk_div < 0x4));
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pclk_div = log2(PERI_ACLK_HZ / PERI_PCLK_HZ);
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assert((1 << pclk_div) * PERI_PCLK_HZ ==
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PERI_ACLK_HZ && (pclk_div < 0x4));
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writel(RK_SETBITS(PERI_SEL_GPLL)
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| RK_CLRSETBITS(PERI_PCLK_DIV_MSK,
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pclk_div << PERI_PCLK_DIV_SHIFT)
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| RK_CLRSETBITS(PERI_HCLK_DIV_MSK,
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hclk_div << PERI_HCLK_DIV_SHIFT)
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| RK_CLRSETBITS(PERI_ACLK_DIV_MSK,
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aclk_div << PERI_ACLK_DIV_SHIFT),
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&cru_ptr->cru_clksel_con[10]);
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/* PLL enter normal-mode */
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@ -26,6 +26,14 @@
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#define GPLL_HZ 594000000
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#define CPLL_HZ 384000000
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#define PD_BUS_ACLK_HZ 148500000
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#define PD_BUS_HCLK_HZ 148500000
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#define PD_BUS_PCLK_HZ 74250000
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#define PERI_ACLK_HZ 148500000
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#define PERI_HCLK_HZ 148500000
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#define PERI_PCLK_HZ 74250000
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void rkclk_init(void);
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void rkclk_configure_spi(unsigned int bus, unsigned int hz);
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void rkclk_ddr_reset(u32 ch, u32 ctl, u32 phy);
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@ -87,6 +87,7 @@ struct rk3288_grf_regs {
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union {
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u32 gpio7a_iomux;
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u32 iomux_pwm0;
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u32 iomux_pwm1;
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};
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u32 gpio7b_iomux;
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union {
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@ -215,4 +216,5 @@ static struct rk3288_sgrf_regs * const rk3288_sgrf = (void *)GRF_SECURE_BASE;
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2 << 2 | 2 << 0)
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#define IOMUX_EMMCPWREN RK_CLRSETBITS(0x3 << 2, 0x2 << 2)
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#define IOMUX_EMMCCMD RK_CLRSETBITS(0x3f, 2 << 4 | 2 << 2 | 2 << 0)
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#define IOMUX_PWM1 RK_SETBITS(1 << 2)
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#endif
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@ -0,0 +1,90 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright 2014 Rockchip Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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#include <console/console.h>
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#include <arch/io.h>
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#include <stdlib.h>
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#include <assert.h>
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#include <timer.h>
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#include <delay.h>
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#include "addressmap.h"
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#include "grf.h"
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#include "soc.h"
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#include "pwm.h"
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#include "clock.h"
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struct pwm_ctl {
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u32 pwm_cnt;
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u32 pwm_period_hpr;
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u32 pwm_duty_lpr;
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u32 pwm_ctrl;
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};
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struct rk3288_pwm_regs {
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struct pwm_ctl pwm[4];
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u32 intsts;
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u32 int_en;
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};
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check_member(rk3288_pwm_regs, int_en, 0x44);
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#define RK_PWM_DISABLE (0 << 0)
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#define RK_PWM_ENABLE (1 << 0)
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#define PWM_ONE_SHOT (0 << 1)
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#define PWM_CONTINUOUS (1 << 1)
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#define RK_PWM_CAPTURE (1 << 2)
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#define PWM_DUTY_POSTIVE (1 << 3)
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#define PWM_DUTY_NEGATIVE (0 << 3)
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#define PWM_INACTIVE_POSTIVE (1 << 4)
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#define PWM_INACTIVE_NEGATIVE (0 << 4)
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#define PWM_OUTPUT_LEFT (0 << 5)
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#define PWM_OUTPUT_CENTER (1 << 5)
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#define PWM_LP_ENABLE (1 << 8)
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#define PWM_LP_DISABLE (0 << 8)
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#define PWM_SEL_SCALE_CLK (1 << 9)
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#define PWM_SEL_SRC_CLK (0 << 9)
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struct rk3288_pwm_regs *rk3288_pwm = (void *)RK_PWM0123_BASE;
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void pwm_init(u32 id, u32 period_ns, u32 duty_ns)
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{
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unsigned long period, duty;
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/*use rk pwm*/
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writel(RK_SETBITS(1 << 0), &rk3288_grf->soc_con2);
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writel(PWM_SEL_SRC_CLK | PWM_OUTPUT_LEFT | PWM_LP_DISABLE |
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PWM_CONTINUOUS | PWM_DUTY_POSTIVE | PWM_INACTIVE_POSTIVE |
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RK_PWM_DISABLE,
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&rk3288_pwm->pwm[id].pwm_ctrl);
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period = (PD_BUS_PCLK_HZ / 1000) * period_ns / USECS_PER_SEC;
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duty = (PD_BUS_PCLK_HZ / 1000) * duty_ns / USECS_PER_SEC;
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writel(period, &rk3288_pwm->pwm[id].pwm_period_hpr);
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writel(duty, &rk3288_pwm->pwm[id].pwm_duty_lpr);
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setbits_le32(&rk3288_pwm->pwm[id].pwm_ctrl, RK_PWM_ENABLE);
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}
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@ -0,0 +1,26 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright 2014 Rockchip Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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#ifndef __SOC_ROCKCHIP_RK3288_PWM_H__
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#define __SOC_ROCKCHIP_RK3288_PWM_H__
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void pwm_init(u32 id, u32 period_ns, u32 duty_ns);
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#endif
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