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soc/intel/cannonlake: Pass coreboot debug interface info to FSP 

coreboot have an option to use legacy UART or LPSS UART. FSP will use the
UART initialized by coreboot and we can choose an option to skip Uart
initialization by FSP.
For this, we need to pass correct debug interface flag to FSP through
which FSP will know which UART port to use. If we don't pass correct
interface information, FSP may try to dump logs on that port and it may
slow down the system.

BUG=none
BRANCH=none
TEST=Compile and boot with coreboot. Check FSP and coreboot logs are
coming on serial port.

Change-Id: I1ebb20c93e2c15ec085538509099de72bc9dd62c
Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31884
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
This commit is contained in:
Maulik V Vaghela 2019-03-13 18:16:01 +05:30 committed by Patrick Georgi
parent 0f681dc5e6
commit bfe4a59bc9
1 changed files with 11 additions and 0 deletions
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11
src/soc/intel/cannonlake/romstage/fsp_params.c
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@ -48,6 +48,17 @@ static void soc_memory_init_params(FSP_M_CONFIG *m_cfg, const config_t *config)
m_cfg->PrmrrSize = config->PrmrrSize; m_cfg->PrmrrSize = config->PrmrrSize;
m_cfg->EnableC6Dram = config->enable_c6dram; m_cfg->EnableC6Dram = config->enable_c6dram;
m_cfg->PcdSerialIoUartNumber = CONFIG_UART_FOR_CONSOLE; m_cfg->PcdSerialIoUartNumber = CONFIG_UART_FOR_CONSOLE;
/*
* PcdDebugInterfaceFlags
* This config will allow coreboot to pass information to the FSP
* regarding which debug interface is being used.
* Debug Interfaces:
* BIT0-RAM, BIT1-Legacy Uart BIT3-USB3, BIT4-LPSS Uart, BIT5-TraceHub
* BIT2 - Not used.
*/
m_cfg->PcdDebugInterfaceFlags =
CONFIG(DRIVERS_UART_8250IO) ? 0x02 : 0x10;
/* Disable Vmx if Vt-d is already disabled */ /* Disable Vmx if Vt-d is already disabled */
if (config->VtdDisable) if (config->VtdDisable)
m_cfg->VmxEnable = 0; m_cfg->VmxEnable = 0;