soc/intel/skylake: Make use of common CSE code for skylake
TEST=Ensures global reset could able to reset system. Change-Id: I11ce1812a5a0aa2da6b414555374460d606e220e Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/22395 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This commit is contained in:
Subrata Banik
Aaron Durbin
parent
4a722f5e2f
commit
bffff54e09
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@ -54,6 +54,7 @@ config CPU_SPECIFIC_OPTIONS
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select SOC_INTEL_COMMON_BLOCK
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select SOC_INTEL_COMMON_BLOCK_CPU
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select SOC_INTEL_COMMON_BLOCK_CPU_MPINIT
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select SOC_INTEL_COMMON_BLOCK_CSE
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select SOC_INTEL_COMMON_BLOCK_EBDA
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select SOC_INTEL_COMMON_BLOCK_FAST_SPI
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select SOC_INTEL_COMMON_BLOCK_GPIO
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@ -18,6 +18,7 @@
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#include <chip.h>
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#include <device/device.h>
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#include <device/pci_def.h>
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#include <intelblocks/cse.h>
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#include <intelblocks/fast_spi.h>
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#include <intelblocks/itss.h>
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#include <intelblocks/lpc_lib.h>
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@ -157,27 +158,6 @@ static void soc_config_tco(void)
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outw(tcocnt, tcobase + TCO1_CNT);
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}
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static void enable_heci(void)
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{
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device_t dev = PCH_DEV_CSE;
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u8 pcireg;
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/* Assign Resources to HECI1 */
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/* Clear BIT 1-2 of Command Register */
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pcireg = pci_read_config8(dev, PCI_COMMAND);
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pcireg &= ~(PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY);
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pci_write_config8(dev, PCI_COMMAND, pcireg);
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/* Program Temporary BAR for HECI1 */
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pci_write_config32(dev, PCI_BASE_ADDRESS_0, HECI1_BASE_ADDRESS);
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pci_write_config32(dev, PCI_BASE_ADDRESS_1, 0x0);
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/* Enable Bus Master and MMIO Space */
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pcireg = pci_read_config8(dev, PCI_COMMAND);
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pcireg |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY;
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pci_write_config8(dev, PCI_COMMAND, pcireg);
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}
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void pch_early_iorange_init(void)
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{
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/* IO Decode Range */
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@ -216,5 +196,6 @@ void pch_early_init(void)
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enable_rtc_upper_bank();
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enable_heci();
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/* initialize Heci interface */
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heci_init(HECI1_BASE_ADDRESS);
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}
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@ -3,7 +3,7 @@
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*
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* Copyright (C) 2008-2009 coresystems GmbH
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* Copyright (C) 2014 Google Inc.
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* Copyright (C) 2016 Intel Corporation.
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* Copyright (C) 2016-2017 Intel Corporation.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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@ -202,47 +202,6 @@ union me_hfs6 {
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} __packed fields;
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};
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/*
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* Management Engine MMIO registers
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*/
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#define MMIO_ME_CB_WW 0x00
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#define MMIO_HOST_CSR 0x04
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union host_csr {
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u32 data;
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struct {
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u32 int_en: 1;
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u32 int_sts: 1;
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u32 int_gen: 1;
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u32 host_ready: 1;
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u32 host_reset: 1;
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u32 rsv: 3;
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u32 host_read_offset: 8;
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u32 host_write_offset: 8;
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u32 me_cir_depth: 8;
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} __packed fields;
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};
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#define MMIO_ME_CB_RW 0x08
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#define MMIO_ME_CSR 0x0C
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union me_csr {
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u32 data;
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struct {
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u32 int_en: 1;
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u32 int_sts: 1;
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u32 int_gen: 1;
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u32 host_ready: 1;
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u32 host_reset: 1;
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u32 rsv: 3;
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u32 me_read_offset: 8;
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u32 me_write_offset: 8;
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u32 me_cir_buff: 8;
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} __packed fields;
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};
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#define MMIO_ME_D0I3 0x800
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/* Reset Request */
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#define MKHI_GLOBAL_RESET 0x0b
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@ -255,23 +214,6 @@ union me_csr {
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#define BIOS_HOST_ADD 0x00
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#define HECI_MKHI_ADD 0x07
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#define MAX_HECI_MESSAGE 5
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#define HECI_TIMEOUT 15000000 /* 15sec */
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#define HECI_SEND_TIMEOUT 5000000 /* 5sec */
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#define HECI_READ_TIMEOUT 5000000 /* 5sec */
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#define HECI_DELAY 1000 /* 1ms */
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union mei_header {
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u32 data;
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struct {
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u32 client_address: 8;
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u32 host_address: 8;
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u32 length: 9;
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u32 reserved: 6;
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u32 is_complete: 1;
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} __packed fields;
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};
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void intel_me_status(void);
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int send_global_reset(void);
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@ -1,7 +1,7 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2016 Intel Corporation.
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* Copyright (C) 2016-2017 Intel Corporation.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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@ -15,40 +15,23 @@
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#include <arch/io.h>
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#include <commonlib/helpers.h>
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#include <compiler.h>
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#include <console/console.h>
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#include <device/pci.h>
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#include <device/pci_def.h>
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#include <device/pci_ids.h>
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#include <intelblocks/cse.h>
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#include <soc/iomap.h>
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#include <soc/me.h>
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#include <soc/pci_devs.h>
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#include <stdint.h>
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#include <compiler.h>
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#include <stdlib.h>
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#include <string.h>
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#include <soc/iomap.h>
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#include <soc/pci_devs.h>
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#include <soc/me.h>
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#include <delay.h>
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#include <timer.h>
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static inline u32 me_read_config32(int offset)
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{
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return pci_read_config32(PCH_DEV_CSE, offset);
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}
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static inline void me_write_config32(int offset, u32 value)
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{
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pci_write_config32(PCH_DEV_CSE, offset, value);
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}
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static inline u32 me_read_mmio32(int offset)
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{
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return read32((void *)(HECI1_BASE_ADDRESS + offset));
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}
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static inline void me_write_mmio32(u16 offset, u32 value)
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{
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write32((void *)(HECI1_BASE_ADDRESS + offset), value);
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}
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/* HFSTS1[3:0] Current Working State Values */
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static const char * const me_cws_values[] = {
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[ME_HFS_CWS_RESET] = "Reset",
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@ -368,291 +351,6 @@ void intel_me_status(void)
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}
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}
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/*
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* Aligning a byte length to length in dwords.
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*/
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static u32 get_dword_length(u32 byte_length)
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{
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return ALIGN_UP(byte_length, sizeof(uint32_t)) / sizeof(uint32_t);
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}
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/*
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* Get remaining message count in dword from circular buffer based on
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* write and read offset.
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*/
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static u32 get_cb_msg_count(u32 data)
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{
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u8 read_offset = data >> 8;
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u8 write_offset = data >> 16;
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return get_dword_length(write_offset - read_offset);
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}
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static int wait_heci_ready(void)
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{
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struct stopwatch sw;
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int timeout = 0;
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union me_csr csr;
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stopwatch_init_msecs_expire(&sw, HECI_TIMEOUT);
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while (1) {
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do {
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csr.data = me_read_mmio32(MMIO_ME_CSR);
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if (csr.fields.host_ready)
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return 0;
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} while (!(timeout = stopwatch_expired(&sw)));
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printk(BIOS_ERR, "ME_RDY bit is not set after 15 sec");
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return -1;
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}
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}
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static int wait_heci_cb_avail(u32 len)
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{
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struct stopwatch sw;
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union host_csr csr;
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csr.data = me_read_mmio32(MMIO_HOST_CSR);
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/*
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* if timeout has happened, return failure as
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* the circular buffer is not empty
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*/
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stopwatch_init_msecs_expire(&sw, HECI_SEND_TIMEOUT);
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/* Must have room for message and message header */
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while (len > (get_dword_length(csr.fields.me_cir_depth) -
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get_cb_msg_count(csr.data))) {
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if (stopwatch_expired(&sw)) {
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printk(BIOS_ERR,
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"Circular Buffer never emptied within 5 sec");
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return -1;
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}
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/* wait before trying again */
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udelay(HECI_DELAY);
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/* read HOST_CSR for next iteration */
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csr.data = me_read_mmio32(MMIO_HOST_CSR);
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}
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return 0;
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}
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static int send_heci_packet(union mei_header *head, u32 len, u32 *payload)
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{
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int sts;
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int index;
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union me_csr csr;
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union host_csr hcsr;
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/*
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* wait until there is sufficient room in CB
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*/
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sts = wait_heci_cb_avail(len + 1);
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if (sts != 0)
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return -1;
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/* Write message header */
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me_write_mmio32(MMIO_ME_CB_WW, head->data);
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/* Write message body */
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for (index = 0; index < len; index++)
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me_write_mmio32(MMIO_ME_CB_WW, payload[index]);
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/* Set Interrupt Generate bit */
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hcsr.data = me_read_mmio32(MMIO_HOST_CSR);
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hcsr.fields.int_gen = 1;
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me_write_mmio32(MMIO_HOST_CSR, hcsr.data);
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/* Check if ME Ready bit is set, if set to 0 then return fatal error */
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csr.data = me_read_mmio32(MMIO_ME_CSR);
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if (csr.fields.host_ready)
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return 0;
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else
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return -1;
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}
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static int recv_heci_packet(union mei_header *head, u32 *packet,
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u32 *packet_size)
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{
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union me_csr csr;
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union host_csr hcsr;
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int rec_msg = 0;
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struct stopwatch sw;
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u32 length, index;
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/* Clear Interrupt Status bit */
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hcsr.data = me_read_mmio32(MMIO_HOST_CSR);
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hcsr.fields.int_sts = 1;
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me_write_mmio32(MMIO_HOST_CSR, hcsr.data);
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/* Check if circular buffer overflow
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* if yes then return fatal error
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*/
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csr.data = me_read_mmio32(MMIO_ME_CSR);
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if (get_cb_msg_count(csr.data) >
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get_dword_length(csr.fields.me_cir_buff))
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return -1;
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/*
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* if timeout has happened, return failure as
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* the circular buffer is not empty
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*/
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stopwatch_init_msecs_expire(&sw, HECI_READ_TIMEOUT);
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/* go until we got message pkt */
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do {
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if (stopwatch_expired(&sw)) {
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printk(BIOS_ERR,
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"Circular Buffer not filled within 5 sec");
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*packet_size = 0;
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return -1;
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}
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csr.data = me_read_mmio32(MMIO_ME_CSR);
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/* Read one message from HECI buffer */
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if (get_cb_msg_count(csr.data) > 0) {
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head->data = me_read_mmio32(MMIO_ME_CB_RW);
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/* calculate the message length in dword */
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length = get_dword_length(head->fields.length);
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if (head->fields.length == 0) {
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*packet_size = 0;
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goto SET_IG;
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}
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/* Make sure, we have enough space to catch all */
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if (head->fields.length <= *packet_size) {
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csr.data = me_read_mmio32(MMIO_ME_CSR);
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/* get complete message into circular buffer */
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while (length > get_cb_msg_count(csr.data)) {
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udelay(HECI_DELAY);
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csr.data = me_read_mmio32(MMIO_ME_CSR);
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}
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/* here is the message */
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for (index = 0; index < length; index++)
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packet[index] =
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me_read_mmio32(MMIO_ME_CB_RW);
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rec_msg = 1;
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*packet_size = head->fields.length;
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} else {
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/* Too small buffer */
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*packet_size = 0;
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return -1;
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}
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}
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} while (!rec_msg);
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/*
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* Check if ME Ready bit is set, if set to 0 then return fatal error
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* because ME might have reset during transaction and we might have
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* read a junk data from CB
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*/
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csr.data = me_read_mmio32(MMIO_ME_CSR);
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if (!(csr.fields.host_ready))
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return -1;
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SET_IG:
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/* Set Interrupt Generate bit */
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hcsr.data = me_read_mmio32(MMIO_HOST_CSR);
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hcsr.fields.int_gen = 1;
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me_write_mmio32(MMIO_HOST_CSR, hcsr.data);
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return 0;
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}
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static int
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send_heci_message(void *msg, int len, u8 hostaddress, u8 clientaddress)
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{
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u8 retry;
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int status = -1;
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u32 cir_buff_depth;
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union host_csr csr;
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union mei_header head;
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int cur = 0;
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u32 slength, rlength;
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for (retry = 0; retry < MAX_HECI_MESSAGE; retry++) {
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if (wait_heci_ready() != 0)
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continue;
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/* HECI is ready */
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csr.data = me_read_mmio32(MMIO_HOST_CSR);
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cir_buff_depth = csr.fields.me_cir_depth;
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head.fields.client_address = clientaddress;
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head.fields.host_address = hostaddress;
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while (len > cur) {
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rlength = get_dword_length(len - cur);
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/*
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* Set the message complete bit if this is last packet
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* in message needs to be "less than" to account for
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* the header OR needs to be exact equal to CB depth
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*/
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if (rlength <= cir_buff_depth)
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head.fields.is_complete = 1;
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else
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head.fields.is_complete = 0;
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/*
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* calculate length for message header
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* header length = smaller of CB buffer or
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* remaining message
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*/
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slength = ((cir_buff_depth <= rlength)
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? ((cir_buff_depth - 1) * 4)
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: (len - cur));
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head.fields.length = slength;
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head.fields.reserved = 0;
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/*
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* send the current packet
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* (cur should be treated as index for message)
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*/
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status = send_heci_packet(&head,
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get_dword_length(head.fields.length), msg);
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if (status != 0)
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break;
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/* update the length information */
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cur += slength;
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msg += cur;
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}
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if (!status)
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break;
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}
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return status;
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}
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static int
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recv_heci_message(void *message, u32 *message_size)
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{
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union mei_header head;
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int cur = 0;
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u8 retry;
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int status = -1;
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int msg_complete = 0;
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u32 pkt_buff;
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for (retry = 0; retry < MAX_HECI_MESSAGE; retry++) {
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if (wait_heci_ready() != 0)
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continue;
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/* HECI is ready */
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while ((cur < *message_size) && (msg_complete == 0)) {
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pkt_buff = *message_size - cur;
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status = recv_heci_packet(&head, message + (cur >> 2),
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&pkt_buff);
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if (status == -1) {
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*message_size = 0;
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break;
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}
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msg_complete = head.fields.is_complete;
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if (pkt_buff == 0) {
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/* if not in middle of msg and msg complete bit
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* is set then this is a valid zero length msg
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*/
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if ((cur == 0) && (msg_complete == 1))
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status = 0;
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else
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status = -1;
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*message_size = 0;
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break;
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||||
}
|
||||
cur += pkt_buff;
|
||||
}
|
||||
if (!status) {
|
||||
*message_size = cur;
|
||||
break;
|
||||
}
|
||||
}
|
||||
return status;
|
||||
}
|
||||
|
||||
static int send_heci_reset_message(void)
|
||||
{
|
||||
int status;
|
||||
|
|
@ -675,19 +373,21 @@ static int send_heci_reset_message(void)
|
|||
.req_origin = GR_ORIGIN_BIOS_POST,
|
||||
.reset_type = GLOBAL_RST_TYPE
|
||||
};
|
||||
u32 reply_size;
|
||||
size_t reply_size;
|
||||
|
||||
status = send_heci_message(&msg, sizeof(msg),
|
||||
BIOS_HOST_ADD, HECI_MKHI_ADD);
|
||||
if (status != 0)
|
||||
heci_reset();
|
||||
|
||||
status = heci_send(&msg, sizeof(msg), BIOS_HOST_ADD, HECI_MKHI_ADD);
|
||||
if (!status)
|
||||
return -1;
|
||||
|
||||
reply_size = sizeof(reply);
|
||||
memset(&reply, 0, reply_size);
|
||||
if (recv_heci_message(&reply, &reply_size) == -1)
|
||||
status = heci_receive(&reply, &reply_size);
|
||||
if (!status)
|
||||
return -1;
|
||||
/* get reply result from HECI MSG */
|
||||
if (reply.result != 0) {
|
||||
if (reply.result) {
|
||||
printk(BIOS_DEBUG, "%s: Exit with Failure\n", __func__);
|
||||
return -1;
|
||||
}
|
||||
|
|
|
|||
Loading…
Reference in New Issue