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soc/amd/common/block/lpc: Set FSP-S/M alignment to 64 when using SPI DMA 

This will enable reading FSP-S/M using the SPI DMA controller.

BUG=B:179699789
TEST=Build guybrush with SPI DMA enabled and verify alignment is set

Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I282b9989d8e95c93603c6f69616a8f236a4e2e35
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59130
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
This commit is contained in:
Raul E Rangel 2021-11-10 13:09:20 -07:00 committed by Paul Fagerburg
parent b139e6b2a3
commit c0025c25f3
1 changed files with 9 additions and 1 deletions
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10
src/soc/amd/common/block/lpc/Kconfig
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@ -16,12 +16,20 @@ config SOC_AMD_COMMON_BLOCK_LPC_SPI_DMA
help
Select this option to enable SPI DMA support.
# The LPC SPI DMA controller requires the destination buffers to be 64 byte
# The LPC SPI DMA controller requires the source and destination to be 64 byte
# aligned.
config CBFS_CACHE_ALIGN
int
default 64 if SOC_AMD_COMMON_BLOCK_LPC_SPI_DMA
config FSP_ALIGNMENT_FSP_S
int
default 64 if SOC_AMD_COMMON_BLOCK_LPC_SPI_DMA
config FSP_ALIGNMENT_FSP_M
int
default 64 if SOC_AMD_COMMON_BLOCK_LPC_SPI_DMA
config SOC_AMD_COMMON_BLOCK_HAS_ESPI
bool
help