Cache 8MB flash instead of 4MB
Also fix the MTRR check to use the total_mtrrs variable instead of a hardcoded 8. Change-Id: I2c5ceb3910cd949f43ecf5b8aff857d6ffe0b1a5 Signed-off-by: Duncan Laurie <dlaurie@google.com> Reviewed-on: http://review.coreboot.org/873 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
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@ -50,6 +50,24 @@ static unsigned int mtrr_msr[] = {
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MTRRfix4K_E0000_MSR, MTRRfix4K_E8000_MSR, MTRRfix4K_F0000_MSR, MTRRfix4K_F8000_MSR,
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};
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/* 2 MTRRS are reserved for the operating system */
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#define BIOS_MTRRS 6
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#define OS_MTRRS 2
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#define MTRRS (BIOS_MTRRS + OS_MTRRS)
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static int total_mtrrs = MTRRS;
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static int bios_mtrrs = BIOS_MTRRS;
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static void detect_var_mtrrs(void)
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{
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msr_t msr;
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msr = rdmsr(MTRRcap_MSR);
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total_mtrrs = msr.lo & 0xff;
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bios_mtrrs = total_mtrrs - OS_MTRRS;
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}
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void enable_fixed_mtrr(void)
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{
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msr_t msr;
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@ -76,8 +94,8 @@ static void set_var_mtrr(
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msr_t base, mask;
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unsigned address_mask_high;
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if (reg >= 8)
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return;
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if (reg >= total_mtrrs)
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return;
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// it is recommended that we disable and enable cache when we
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// do this.
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@ -169,28 +187,6 @@ static inline unsigned int fls(unsigned int x)
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* or a 156MB (128MB + 32MB - 4MB SMA) example:
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* ramsize = 156MB == 128MB WB (at 0MB) + 32MB WB (at 128MB) + 4MB UC (at 156MB)
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*/
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/* 2 MTRRS are reserved for the operating system */
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#if 1
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#define BIOS_MTRRS 6
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#define OS_MTRRS 2
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#else
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#define BIOS_MTRRS 8
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#define OS_MTRRS 0
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#endif
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#define MTRRS (BIOS_MTRRS + OS_MTRRS)
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static int total_mtrrs = MTRRS;
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static int bios_mtrrs = BIOS_MTRRS;
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static void detect_var_mtrrs(void)
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{
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msr_t msr;
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msr = rdmsr(MTRRcap_MSR);
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total_mtrrs = msr.lo & 0xff;
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bios_mtrrs = total_mtrrs - 2;
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}
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static void set_fixed_mtrrs(unsigned int first, unsigned int last, unsigned char type)
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{
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@ -504,7 +500,7 @@ void x86_setup_var_mtrrs(unsigned int address_bits, unsigned int above4gb)
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* complete ROM now that we actually have RAM.
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*/
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if (boot_cpu() && (acpi_slp_type != 3)) {
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set_var_mtrr(total_mtrrs-1, (4096-4)*1024, 4*1024,
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set_var_mtrr(total_mtrrs - 1, (4096 - 8)*1024, 8 * 1024,
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MTRR_TYPE_WRPROT, address_bits);
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}
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#endif
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