cpu/intel: Use CPU_INTEL_COMMON_TIMEBASE

Change-Id: I0e7159039751a88d86b6c343be5f085e6e15570a
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31342
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>

src/cpu/intel/haswell/Kconfig

@@ -22,6 +22,7 @@ config CPU_SPECIFIC_OPTIONS
 	select CPU_INTEL_FIRMWARE_INTERFACE_TABLE
 	select PARALLEL_MP
 	select CPU_INTEL_COMMON
+	select CPU_INTEL_COMMON_TIMEBASE
 	select NO_FIXED_XIP_ROM_SIZE
 
 config SMM_TSEG_SIZE

src/cpu/intel/haswell/Makefile.inc

@@ -1,27 +1,19 @@
 ramstage-y += haswell_init.c
-ramstage-y += tsc_freq.c
 romstage-y += romstage.c
-romstage-y += tsc_freq.c
 romstage-y += ../car/romstage.c
 
-postcar-y += tsc_freq.c
-
 ramstage-y += acpi.c
 ramstage-$(CONFIG_HAVE_SMI_HANDLER) += smmrelocate.c
 
 smm-y += finalize.c
-smm-y += tsc_freq.c
 
 bootblock-y += ../car/non-evict/cache_as_ram.S
 bootblock-y += ../car/bootblock.c
 bootblock-y += ../../x86/early_reset.S
 bootblock-y += bootblock.c
-bootblock-y += tsc_freq.c
 
 postcar-y += ../car/non-evict/exit_car.S
 
-verstage-y += tsc_freq.c
-
 subdirs-y += ../../x86/tsc
 subdirs-y += ../../x86/mtrr
 subdirs-y += ../../x86/lapic

src/cpu/intel/haswell/tsc_freq.c

@@ -1,25 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#include <stdint.h>
-#include <cpu/x86/msr.h>
-#include <cpu/x86/tsc.h>
-#include "cpu/intel/haswell/haswell.h"
-
-unsigned long tsc_freq_mhz(void)
-{
-	msr_t platform_info;
-
-	platform_info = rdmsr(MSR_PLATFORM_INFO);
-	return HASWELL_BCLK * ((platform_info.lo >> 8) & 0xff);
-}

src/cpu/intel/model_2065x/Kconfig

@@ -19,6 +19,7 @@ config CPU_SPECIFIC_OPTIONS
 	#select AP_IN_SIPI_WAIT
 	select TSC_SYNC_MFENCE
 	select CPU_INTEL_COMMON
+	select CPU_INTEL_COMMON_TIMEBASE
 	select NO_FIXED_XIP_ROM_SIZE
 	select PARALLEL_MP
 

src/cpu/intel/model_2065x/Makefile.inc

@@ -10,11 +10,6 @@ subdirs-y += ../../x86/smm
 subdirs-y += ../smm/gen1
 subdirs-y += ../common
 
-ramstage-y += tsc_freq.c
-romstage-y += tsc_freq.c
-postcar-y += tsc_freq.c
-smm-y += tsc_freq.c
-
 ramstage-y += acpi.c
 
 smm-y += finalize.c

src/cpu/intel/model_2065x/tsc_freq.c

@@ -1,25 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#include <stdint.h>
-#include <cpu/x86/msr.h>
-#include <cpu/x86/tsc.h>
-#include "model_2065x.h"
-
-unsigned long tsc_freq_mhz(void)
-{
-	msr_t platform_info;
-
-	platform_info = rdmsr(MSR_PLATFORM_INFO);
-	return NEHALEM_BCLK * ((platform_info.lo >> 8) & 0xff);
-}

src/cpu/intel/model_206ax/Kconfig

@@ -19,6 +19,7 @@ config CPU_SPECIFIC_OPTIONS
 	#select AP_IN_SIPI_WAIT
 	select TSC_SYNC_MFENCE
 	select CPU_INTEL_COMMON
+	select CPU_INTEL_COMMON_TIMEBASE
 	select PARALLEL_MP
 	select NO_FIXED_XIP_ROM_SIZE
 

src/cpu/intel/model_206ax/Makefile.inc

@@ -17,11 +17,6 @@ ramstage-y += common.c
 romstage-y += common.c
 smm-y += common.c
 
-ramstage-y += tsc_freq.c
-romstage-y += tsc_freq.c
-postcar-y += tsc_freq.c
-smm-y += tsc_freq.c
-
 smm-y += finalize.c
 
 cpu_microcode_bins += $(wildcard 3rdparty/intel-microcode/intel-ucode/06-2a-*)

src/cpu/intel/model_206ax/tsc_freq.c

@@ -1,25 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#include <stdint.h>
-#include <cpu/x86/msr.h>
-#include <cpu/x86/tsc.h>
-#include "model_206ax.h"
-
-unsigned long tsc_freq_mhz(void)
-{
-	msr_t platform_info;
-
-	platform_info = rdmsr(MSR_PLATFORM_INFO);
-	return SANDYBRIDGE_BCLK * ((platform_info.lo >> 8) & 0xff);
-}