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arch/riscv: Rename `stages.c` to `romstage.c` 

It's only used for romstage and is incompatible to ramstages. The latter
get `cbmem_top` passed as a third argument now.

Also drop comments that don't apply to this file anymore.

Change-Id: Ibabb022860f5d141ab35922f30e856da8473b529
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36611
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
This commit is contained in:
Nico Huber 2019-11-04 16:32:01 +01:00 committed by Patrick Georgi
parent 214661e00c
commit c01d0920bb
2 changed files with 1 additions and 10 deletions
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2
src/arch/riscv/Makefile.inc
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@ -98,7 +98,7 @@ endif #CONFIG_ARCH_BOOTBLOCK_RISCV
ifeq ($(CONFIG_ARCH_ROMSTAGE_RISCV),y) ifeq ($(CONFIG_ARCH_ROMSTAGE_RISCV),y)
romstage-y += boot.c romstage-y += boot.c
romstage-y += stages.c romstage-y += romstage.c
romstage-y += misc.c romstage-y += misc.c
romstage-$(ARCH_RISCV_PMP) += pmp.c romstage-$(ARCH_RISCV_PMP) += pmp.c
romstage-y += smp.c romstage-y += smp.c

9
src/arch/riscv/stages.c → src/arch/riscv/romstage.c
View File

@ -14,10 +14,6 @@
*/ */
/* /*
* This file contains entry/exit functions for each stage during coreboot
* execution (bootblock entry and ramstage exit will depend on external
* loading).
*
* Entry points must be placed at the location the previous stage jumps * Entry points must be placed at the location the previous stage jumps
* to (the lowest address in the stage image). This is done by giving * to (the lowest address in the stage image). This is done by giving
* stage_entry() its own section in .text and placing it first in the * stage_entry() its own section in .text and placing it first in the
@ -31,11 +27,6 @@
void stage_entry(int hart_id, void *fdt) void stage_entry(int hart_id, void *fdt)
{ {
/*
* Save the FDT pointer before entering ramstage, because mscratch
* might be overwritten in the trap handler, and there is code in
* ramstage that generates misaligned access faults.
*/
HLS()->hart_id = hart_id; HLS()->hart_id = hart_id;
HLS()->fdt = fdt; HLS()->fdt = fdt;
smp_pause(CONFIG_RISCV_WORKING_HARTID); smp_pause(CONFIG_RISCV_WORKING_HARTID);