arch/riscv: Rename `stages.c` to `romstage.c`

It's only used for romstage and is incompatible to ramstages. The latter
get `cbmem_top` passed as a third argument now.

Also drop comments that don't apply to this file anymore.

Change-Id: Ibabb022860f5d141ab35922f30e856da8473b529
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36611
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>

src/arch/riscv/Makefile.inc

@@ -98,7 +98,7 @@ endif #CONFIG_ARCH_BOOTBLOCK_RISCV
 ifeq ($(CONFIG_ARCH_ROMSTAGE_RISCV),y)
 
 romstage-y += boot.c
-romstage-y += stages.c
+romstage-y += romstage.c
 romstage-y += misc.c
 romstage-$(ARCH_RISCV_PMP) += pmp.c
 romstage-y += smp.c

src/arch/riscv/romstage.c

@@ -14,10 +14,6 @@
  */
 
 /*
- * This file contains entry/exit functions for each stage during coreboot
- * execution (bootblock entry and ramstage exit will depend on external
- * loading).
- *
  * Entry points must be placed at the location the previous stage jumps
  * to (the lowest address in the stage image). This is done by giving
  * stage_entry() its own section in .text and placing it first in the
@@ -31,11 +27,6 @@
 
 void stage_entry(int hart_id, void *fdt)
 {
-	/*
-	 * Save the FDT pointer before entering ramstage, because mscratch
-	 * might be overwritten in the trap handler, and there is code in
-	 * ramstage that generates misaligned access faults.
-	 */
 	HLS()->hart_id = hart_id;
 	HLS()->fdt = fdt;
 	smp_pause(CONFIG_RISCV_WORKING_HARTID);