diff --git a/src/southbridge/amd/agesa/hudson/early_setup.c b/src/southbridge/amd/agesa/hudson/early_setup.c
index 1cdaa056b8..a5f46bec24 100644
--- a/src/southbridge/amd/agesa/hudson/early_setup.c
+++ b/src/southbridge/amd/agesa/hudson/early_setup.c
@@ -94,7 +94,7 @@ int s3_save_nvram_early(u32 dword, int size, int  nvram_pos)
 	int i;
 	printk(BIOS_DEBUG, "Writing %x of size %d to nvram pos: %d\n", dword, size, nvram_pos);
 
-	for (i = 0; i<size; i++) {
+	for (i = 0; i < size; i++) {
 		outb(nvram_pos, BIOSRAM_INDEX);
 		outb((dword >>(8 * i)) & 0xff , BIOSRAM_DATA);
 		nvram_pos++;
@@ -107,7 +107,7 @@ int s3_load_nvram_early(int size, u32 *old_dword, int nvram_pos)
 {
 	u32 data = *old_dword;
 	int i;
-	for (i = 0; i<size; i++) {
+	for (i = 0; i < size; i++) {
 		outb(nvram_pos, BIOSRAM_INDEX);
 		data &= ~(0xff << (i * 8));
 		data |= inb(BIOSRAM_DATA) << (i *8);
diff --git a/src/southbridge/amd/agesa/hudson/enable_usbdebug.c b/src/southbridge/amd/agesa/hudson/enable_usbdebug.c
index 5874c37691..fce7f5b33b 100644
--- a/src/southbridge/amd/agesa/hudson/enable_usbdebug.c
+++ b/src/southbridge/amd/agesa/hudson/enable_usbdebug.c
@@ -26,9 +26,9 @@
 
 pci_devfn_t pci_ehci_dbg_dev(unsigned int hcd_idx)
 {
-	if (hcd_idx==3)
+	if (hcd_idx == 3)
 		return PCI_DEV(0, 0x16, 2);
-	else if (hcd_idx==2)
+	else if (hcd_idx == 2)
 		return PCI_DEV(0, 0x13, 2);
 	else
 		return PCI_DEV(0, 0x12, 2);
diff --git a/src/southbridge/amd/agesa/hudson/imc.c b/src/southbridge/amd/agesa/hudson/imc.c
index 4da6814c68..049eca95ff 100644
--- a/src/southbridge/amd/agesa/hudson/imc.c
+++ b/src/southbridge/amd/agesa/hudson/imc.c
@@ -66,12 +66,12 @@ void enable_imc_thermal_zone(void)
 	regs[0] = 0;
 	regs[1] = 0;
 	FunNum = Fun_80;
-	for (i=0; i<=1; i++)
+	for (i = 0; i <= 1; i++)
 		WriteECmsg(MSG_REG0 + i, AccessWidth8, &regs[i], &StdHeader);
 	WriteECmsg(MSG_SYS_TO_IMC, AccessWidth8, &FunNum, &StdHeader);     // function number
 	WaitForEcLDN9MailboxCmdAck(&StdHeader);
 
-	for (i=2; i<=9; i++)
+	for (i = 2; i <= 9; i++)
 		ReadECmsg(MSG_REG0 + i, AccessWidth8, &regs[i], &StdHeader);
 
 	/* enable thermal zone 0 */
@@ -79,7 +79,7 @@ void enable_imc_thermal_zone(void)
 	regs[0] = 0;
 	regs[1] = 0;
 	FunNum = Fun_81;
-	for (i=0; i<=9; i++)
+	for (i = 0; i <= 9; i++)
 		WriteECmsg(MSG_REG0 + i, AccessWidth8, &regs[i], &StdHeader);
 	WriteECmsg(MSG_SYS_TO_IMC, AccessWidth8, &FunNum, &StdHeader);     // function number
 	WaitForEcLDN9MailboxCmdAck(&StdHeader);
diff --git a/src/southbridge/amd/agesa/hudson/ramtop.c b/src/southbridge/amd/agesa/hudson/ramtop.c
index e76a0c4249..567cd12979 100644
--- a/src/southbridge/amd/agesa/hudson/ramtop.c
+++ b/src/southbridge/amd/agesa/hudson/ramtop.c
@@ -33,7 +33,7 @@ void backup_top_of_ram(uint64_t ramtop)
 {
 	u32 dword = (u32) ramtop;
 	int nvram_pos = 0xf8, i; /* temp */
-	for (i = 0; i<4; i++) {
+	for (i = 0; i < 4; i++) {
 		outb(nvram_pos, BIOSRAM_INDEX);
 		outb((dword >>(8 * i)) & 0xff , BIOSRAM_DATA);
 		nvram_pos++;
@@ -47,7 +47,7 @@ unsigned long get_top_of_ram(void)
 	int xnvram_pos = 0xf8, xi;
 	if (acpi_get_sleep_type() != 3)
 		return 0;
-	for (xi = 0; xi<4; xi++) {
+	for (xi = 0; xi < 4; xi++) {
 		outb(xnvram_pos, BIOSRAM_INDEX);
 		xdata &= ~(0xff << (xi * 8));
 		xdata |= inb(BIOSRAM_DATA) << (xi *8);
diff --git a/src/southbridge/amd/amd8111/amd8111_smbus.h b/src/southbridge/amd/amd8111/amd8111_smbus.h
index bf0b03791f..f82bb19e8e 100644
--- a/src/southbridge/amd/amd8111/amd8111_smbus.h
+++ b/src/southbridge/amd/amd8111/amd8111_smbus.h
@@ -267,7 +267,7 @@ static int do_smbus_block_read(unsigned smbus_io_base, unsigned device, unsigned
 	}
 
 	/* read data block */
-	for (i=0; i<msglen && i<bytes; i++) {
+	for (i = 0; i < msglen && i < bytes; i++) {
 		buf[i] = inw(smbus_io_base + SMBHSTFIFO) & 0xff;
 	}
 	/* empty fifo */
@@ -305,7 +305,7 @@ static int do_smbus_block_write(unsigned smbus_io_base, unsigned device, unsigne
 	outw(bytes, smbus_io_base + SMBHSTDAT);
 
 	/* set the data block */
-	for (i=0; i<bytes; i++) {
+	for (i = 0; i < bytes; i++) {
 		outw(buf[i], smbus_io_base + SMBHSTFIFO);
 	}
 
diff --git a/src/southbridge/amd/cimx/sb700/lpc.c b/src/southbridge/amd/cimx/sb700/lpc.c
index 60c07cbdd8..1639f087a1 100644
--- a/src/southbridge/amd/cimx/sb700/lpc.c
+++ b/src/southbridge/amd/cimx/sb700/lpc.c
@@ -29,7 +29,7 @@ void backup_top_of_ram(uint64_t ramtop)
 {
 	u32 dword = (u32) ramtop;
 	int nvram_pos = 0xfc, i;
-	for (i = 0; i<4; i++) {
+	for (i = 0; i < 4; i++) {
 		outb(nvram_pos, BIOSRAM_INDEX);
 		outb((dword >>(8 * i)) & 0xff , BIOSRAM_DATA);
 		nvram_pos++;
diff --git a/src/southbridge/amd/cimx/sb800/ramtop.c b/src/southbridge/amd/cimx/sb800/ramtop.c
index c1ea53e66d..44a49600ac 100644
--- a/src/southbridge/amd/cimx/sb800/ramtop.c
+++ b/src/southbridge/amd/cimx/sb800/ramtop.c
@@ -33,7 +33,7 @@ void backup_top_of_ram(uint64_t ramtop)
 {
 	u32 dword = (u32) ramtop;
 	int nvram_pos = 0xf8, i; /* temp */
-	for (i = 0; i<4; i++) {
+	for (i = 0; i < 4; i++) {
 		outb(nvram_pos, BIOSRAM_INDEX);
 		outb((dword >>(8 * i)) & 0xff , BIOSRAM_DATA);
 		nvram_pos++;
@@ -47,7 +47,7 @@ unsigned long get_top_of_ram(void)
 	int xnvram_pos = 0xf8, xi;
 	if (acpi_get_sleep_type() != 3)
 		return 0;
-	for (xi = 0; xi<4; xi++) {
+	for (xi = 0; xi < 4; xi++) {
 		outb(xnvram_pos, BIOSRAM_INDEX);
 		xdata &= ~(0xff << (xi * 8));
 		xdata |= inb(BIOSRAM_DATA) << (xi *8);
diff --git a/src/southbridge/amd/cs5535/chipsetinit.c b/src/southbridge/amd/cs5535/chipsetinit.c
index a6c0084087..1b7fe5dd80 100644
--- a/src/southbridge/amd/cs5535/chipsetinit.c
+++ b/src/southbridge/amd/cs5535/chipsetinit.c
@@ -22,11 +22,11 @@ struct msrinit {
 
 /*  Master Configuration Register for Bus Masters. */
 static struct msrinit SB_MASTER_CONF_TABLE[] = {
-	{ USB1_SB_GLD_MSR_CONF,	{.hi=0,.lo=0x00008f000} },	/*  NOTE: Must be 1st entry in table */
-	{ USB2_SB_GLD_MSR_CONF,	{.hi=0,.lo=0x00008f000} },
-	{ ATA_SB_GLD_MSR_CONF,	{.hi=0,.lo=0x00048f000} },
-	{ AC97_SB_GLD_MSR_CONF,	{.hi=0,.lo=0x00008f000} },
-	{ MDD_SB_GLD_MSR_CONF,	{.hi=0,.lo=0x00000f000} },
+	{ USB1_SB_GLD_MSR_CONF,	{.hi = 0,.lo = 0x00008f000} },	/*  NOTE: Must be 1st entry in table */
+	{ USB2_SB_GLD_MSR_CONF,	{.hi = 0,.lo = 0x00008f000} },
+	{ ATA_SB_GLD_MSR_CONF,	{.hi = 0,.lo = 0x00048f000} },
+	{ AC97_SB_GLD_MSR_CONF,	{.hi = 0,.lo = 0x00008f000} },
+	{ MDD_SB_GLD_MSR_CONF,	{.hi = 0,.lo = 0x00000f000} },
 /* GLPCI_SB_GLD_MSR_CONF,	0x0FFFFFFFF*/
 /* GLCP_SB_GLD_MSR_CONF,	0x0FFFFFFFF*/
 /* GLIU_SB_GLD_MSR_CONF,	0x0*/
@@ -35,15 +35,15 @@ static struct msrinit SB_MASTER_CONF_TABLE[] = {
 
 /*  5535_A3 Clock Gating*/
 static struct msrinit CS5535_CLOCK_GATING_TABLE[] = {
-	{ USB1_SB_GLD_MSR_PM,	{.hi=0, .lo=0x000000005} },
-	{ USB2_SB_GLD_MSR_PM,	{.hi=0, .lo=0x000000005} },
-	{ GLIU_SB_GLD_MSR_PM,	{.hi=0, .lo=0x000000004} },
-	{ GLPCI_SB_GLD_MSR_PM,	{.hi=0, .lo=0x000000005} },
-	{ GLCP_SB_GLD_MSR_PM,	{.hi=0, .lo=0x000000004} },
-	{ MDD_SB_GLD_MSR_PM,	{.hi=0, .lo=0x050554111} },
-	{ ATA_SB_GLD_MSR_PM,	{.hi=0, .lo=0x000000005} },
-	{ AC97_SB_GLD_MSR_PM,	{.hi=0, .lo=0x000000005} },
-	{ 0,			{.hi=0, .lo=0x000000000} }
+	{ USB1_SB_GLD_MSR_PM,	{.hi = 0, .lo = 0x000000005} },
+	{ USB2_SB_GLD_MSR_PM,	{.hi = 0, .lo = 0x000000005} },
+	{ GLIU_SB_GLD_MSR_PM,	{.hi = 0, .lo = 0x000000004} },
+	{ GLPCI_SB_GLD_MSR_PM,	{.hi = 0, .lo = 0x000000005} },
+	{ GLCP_SB_GLD_MSR_PM,	{.hi = 0, .lo = 0x000000004} },
+	{ MDD_SB_GLD_MSR_PM,	{.hi = 0, .lo = 0x050554111} },
+	{ ATA_SB_GLD_MSR_PM,	{.hi = 0, .lo = 0x000000005} },
+	{ AC97_SB_GLD_MSR_PM,	{.hi = 0, .lo = 0x000000005} },
+	{ 0,			{.hi = 0, .lo = 0x000000000} }
 };
 
 #ifdef UNUSED_CODE
diff --git a/src/southbridge/amd/cs5535/cs5535.c b/src/southbridge/amd/cs5535/cs5535.c
index 3f6e48ff55..2868683df7 100644
--- a/src/southbridge/amd/cs5535/cs5535.c
+++ b/src/southbridge/amd/cs5535/cs5535.c
@@ -56,9 +56,9 @@ static void dump_south(struct device *dev)
 {
 	int i, j;
 
-	for (i=0; i<256; i+=16) {
+	for (i = 0; i < 256; i+=16) {
 		printk(BIOS_DEBUG, "0x%02x: ", i);
-		for (j=0; j<16; j++)
+		for (j = 0; j < 16; j++)
 			printk(BIOS_DEBUG, "%02x ", pci_read_config8(dev, i+j));
 		printk(BIOS_DEBUG, "\n");
 	}
diff --git a/src/southbridge/amd/cs5536/pirq.c b/src/southbridge/amd/cs5536/pirq.c
index 4bb33d512e..0352dbc1ef 100644
--- a/src/southbridge/amd/cs5536/pirq.c
+++ b/src/southbridge/amd/cs5536/pirq.c
@@ -19,7 +19,7 @@
 #include <device/pci.h>
 #include <device/pci_ids.h>
 
-#if (CONFIG_PIRQ_ROUTE==1 && CONFIG_GENERATE_PIRQ_TABLE==1)
+#if (CONFIG_PIRQ_ROUTE == 1 && CONFIG_GENERATE_PIRQ_TABLE == 1)
 void pirq_assign_irqs(const unsigned char pIntAtoD[4])
 {
 	device_t pdev;
diff --git a/src/southbridge/amd/pi/hudson/early_setup.c b/src/southbridge/amd/pi/hudson/early_setup.c
index dce16206f0..29809f1aec 100644
--- a/src/southbridge/amd/pi/hudson/early_setup.c
+++ b/src/southbridge/amd/pi/hudson/early_setup.c
@@ -149,7 +149,7 @@ int s3_save_nvram_early(u32 dword, int size, int  nvram_pos)
 	int i;
 	printk(BIOS_DEBUG, "Writing %x of size %d to nvram pos: %d\n", dword, size, nvram_pos);
 
-	for (i = 0; i<size; i++) {
+	for (i = 0; i < size; i++) {
 		outb(nvram_pos, BIOSRAM_INDEX);
 		outb((dword >>(8 * i)) & 0xff , BIOSRAM_DATA);
 		nvram_pos++;
@@ -162,7 +162,7 @@ int s3_load_nvram_early(int size, u32 *old_dword, int nvram_pos)
 {
 	u32 data = *old_dword;
 	int i;
-	for (i = 0; i<size; i++) {
+	for (i = 0; i < size; i++) {
 		outb(nvram_pos, BIOSRAM_INDEX);
 		data &= ~(0xff << (i * 8));
 		data |= inb(BIOSRAM_DATA) << (i *8);
diff --git a/src/southbridge/amd/pi/hudson/enable_usbdebug.c b/src/southbridge/amd/pi/hudson/enable_usbdebug.c
index 84691eb500..787da6b676 100644
--- a/src/southbridge/amd/pi/hudson/enable_usbdebug.c
+++ b/src/southbridge/amd/pi/hudson/enable_usbdebug.c
@@ -26,9 +26,9 @@
 
 pci_devfn_t pci_ehci_dbg_dev(unsigned int hcd_idx)
 {
-	if (hcd_idx==3)
+	if (hcd_idx == 3)
 		return PCI_DEV(0, 0x16, 0);
-	else if (hcd_idx==2)
+	else if (hcd_idx == 2)
 		return PCI_DEV(0, 0x13, 0);
 	else
 		return PCI_DEV(0, 0x12, 0);
diff --git a/src/southbridge/amd/rs780/gfx.c b/src/southbridge/amd/rs780/gfx.c
index 78cb837b8d..c2b3d3a8c2 100644
--- a/src/southbridge/amd/rs780/gfx.c
+++ b/src/southbridge/amd/rs780/gfx.c
@@ -110,7 +110,7 @@ MMIORANGE MMIO[8], CreativeMMIO[8];
 static MMIORANGE* AllocMMIO(MMIORANGE* pMMIO)
 {
 	int i;
-	for (i=0; i<8; i++) {
+	for (i = 0; i < 8; i++) {
 		if (pMMIO[i].Limit == 0)
 				return &pMMIO[i];
 	}
@@ -127,7 +127,7 @@ static u32 SetMMIO(u32 Base, u32 Limit, u8 Attribute, MMIORANGE *pMMIO)
 {
 	int i;
 	MMIORANGE * TempRange;
-	for (i=0; i<8; i++) {
+	for (i = 0; i < 8; i++) {
 		if (pMMIO[i].Attribute != Attribute && Base >= pMMIO[i].Base && Limit <= pMMIO[i].Limit) {
 			TempRange = AllocMMIO(pMMIO);
 			if (TempRange == 0) return 0x80000000;
@@ -148,12 +148,12 @@ static u32 SetMMIO(u32 Base, u32 Limit, u8 Attribute, MMIORANGE *pMMIO)
 static u8 FinalizeMMIO(MMIORANGE *pMMIO)
 {
 	int i, j, n = 0;
-	for (i=0; i<8; i++) {
+	for (i = 0; i < 8; i++) {
 		if (pMMIO[i].Base == pMMIO[i].Limit) {
 			FreeMMIO(&pMMIO[i]);
 			continue;
 		}
-		for (j=0; j<i; j++) {
+		for (j = 0; j < i; j++) {
 			if (i!=j && pMMIO[i].Attribute == pMMIO[j].Attribute) {
 				if (pMMIO[i].Base == pMMIO[j].Limit) {
 					pMMIO[j].Limit = pMMIO[i].Limit;
@@ -166,7 +166,7 @@ static u8 FinalizeMMIO(MMIORANGE *pMMIO)
 			}
 		}
 	}
-	for (i=0; i<8; i++) {
+	for (i = 0; i < 8; i++) {
 		if (pMMIO[i].Limit != 0) n++;
 	}
 	return n;
@@ -344,7 +344,7 @@ static void internal_gfx_pci_dev_init(struct device *dev)
 
 	/* Clear vgainfo. */
 	bpointer = (unsigned char *) &vgainfo;
-	for (i=0; i<sizeof(ATOM_INTEGRATED_SYSTEM_INFO_V2); i++) {
+	for (i = 0; i < sizeof(ATOM_INTEGRATED_SYSTEM_INFO_V2); i++) {
 		*bpointer = 0;
 		bpointer++;
 	}
@@ -448,7 +448,7 @@ static void internal_gfx_pci_dev_init(struct device *dev)
 	// Side port support is incomplete, do not use it
 	// These parameters must match the motherboard
 	vgainfo.ulBootUpSidePortClock = 667*100;
-	vgainfo.ucMemoryType = 3;  // 3=ddr3 sp mem, 2=ddr2 sp mem
+	vgainfo.ucMemoryType = 3;  // 3 = ddr3 sp mem, 2 = ddr2 sp mem
 	vgainfo.ulMinSidePortClock = 333*100;
 #endif
 
@@ -628,7 +628,7 @@ static void internal_gfx_pci_dev_init(struct device *dev)
 
 	/* Transfer the Table to VBIOS. */
 	pointer = (u32 *)&vgainfo;
-	for (i=0; i<sizeof(ATOM_INTEGRATED_SYSTEM_INFO_V2); i+=4) {
+	for (i = 0; i < sizeof(ATOM_INTEGRATED_SYSTEM_INFO_V2); i+=4) {
 #if CONFIG_GFXUMA
 		*GpuF0MMReg = 0x80000000 + uma_memory_size - 512 + i;
 #else
@@ -662,12 +662,12 @@ static void internal_gfx_pci_dev_init(struct device *dev)
 
 	/* clear MMIO and CreativeMMIO. */
 	bpointer = (unsigned char *)MMIO;
-	for (i=0; i<sizeof(MMIO); i++) {
+	for (i = 0; i < sizeof(MMIO); i++) {
 		*bpointer = 0;
 		bpointer++;
 	}
 	bpointer = (unsigned char *)CreativeMMIO;
-	for (i=0; i<sizeof(CreativeMMIO); i++) {
+	for (i = 0; i < sizeof(CreativeMMIO); i++) {
 		*bpointer = 0;
 		bpointer++;
 	}
@@ -943,11 +943,11 @@ static void rs780_internal_gfx_enable(device_t dev)
 	/* set_nbmc_enable_bits(nb_dev, 0xac, ~(0xfffffff0), 0x0b); */
 
 	/* Init PM timing. */
-	for (i=0; i<4; i++) {
+	for (i = 0; i < 4; i++) {
 		l_dword = nbmc_read_index(nb_dev, 0xa0+i);
 		nbmc_write_index(nb_dev, 0xc8+i, l_dword);
 	}
-	for (i=0; i<4; i++) {
+	for (i = 0; i < 4; i++) {
 		l_dword = nbmc_read_index(nb_dev, 0xa8+i);
 		nbmc_write_index(nb_dev, 0xcc+i, l_dword);
 	}
diff --git a/src/southbridge/amd/sb600/hda.c b/src/southbridge/amd/sb600/hda.c
index 748610ca65..88b242e52e 100644
--- a/src/southbridge/amd/sb600/hda.c
+++ b/src/southbridge/amd/sb600/hda.c
@@ -176,7 +176,7 @@ static int wait_for_ready(void *base)
 	int timeout = 50;
 
 	while (timeout--) {
-		u32 dword=read32(base +  HDA_ICII_REG);
+		u32 dword = read32(base +  HDA_ICII_REG);
 		if (!(dword & HDA_ICII_BUSY))
 			return 0;
 		udelay(1);
diff --git a/src/southbridge/amd/sb700/early_setup.c b/src/southbridge/amd/sb700/early_setup.c
index 1aa7be0cd6..ea7eb27161 100644
--- a/src/southbridge/amd/sb700/early_setup.c
+++ b/src/southbridge/amd/sb700/early_setup.c
@@ -814,7 +814,7 @@ int s3_save_nvram_early(u32 dword, int size, int  nvram_pos)
 	int i;
 	printk(BIOS_DEBUG, "Writing %x of size %d to nvram pos: %d\n", dword, size, nvram_pos);
 
-	for (i = 0; i<size; i++) {
+	for (i = 0; i < size; i++) {
 		outb(nvram_pos, BIOSRAM_INDEX);
 		outb((dword >>(8 * i)) & 0xff , BIOSRAM_DATA);
 		nvram_pos++;
@@ -827,7 +827,7 @@ int s3_load_nvram_early(int size, u32 *old_dword, int nvram_pos)
 {
 	u32 data = *old_dword;
 	int i;
-	for (i = 0; i<size; i++) {
+	for (i = 0; i < size; i++) {
 		outb(nvram_pos, BIOSRAM_INDEX);
 		data &= ~(0xff << (i * 8));
 		data |= inb(BIOSRAM_DATA) << (i *8);
@@ -865,7 +865,7 @@ unsigned long get_top_of_ram(void)
 	int xnvram_pos = 0xfc, xi;
 	if (acpi_get_sleep_type() != 3)
 		return 0;
-	for (xi = 0; xi<4; xi++) {
+	for (xi = 0; xi < 4; xi++) {
 		outb(xnvram_pos, BIOSRAM_INDEX);
 		xdata &= ~(0xff << (xi * 8));
 		xdata |= inb(BIOSRAM_DATA) << (xi *8);
diff --git a/src/southbridge/amd/sb700/enable_usbdebug.c b/src/southbridge/amd/sb700/enable_usbdebug.c
index 2b0f8cc7a6..22f730f4ed 100644
--- a/src/southbridge/amd/sb700/enable_usbdebug.c
+++ b/src/southbridge/amd/sb700/enable_usbdebug.c
@@ -27,7 +27,7 @@
 
 pci_devfn_t pci_ehci_dbg_dev(unsigned int hcd_idx)
 {
-	if (hcd_idx==2)
+	if (hcd_idx == 2)
 		return PCI_DEV(0, 0x13, 2);
 	else
 		return PCI_DEV(0, 0x12, 2);
diff --git a/src/southbridge/amd/sb700/hda.c b/src/southbridge/amd/sb700/hda.c
index 8497cc5da2..22537222ec 100644
--- a/src/southbridge/amd/sb700/hda.c
+++ b/src/southbridge/amd/sb700/hda.c
@@ -98,7 +98,7 @@ static int wait_for_ready(void *base)
 	int timeout = 50;
 
 	while (timeout--) {
-		u32 dword=read32(base +  HDA_ICII_REG);
+		u32 dword = read32(base +  HDA_ICII_REG);
 		if (!(dword & HDA_ICII_BUSY))
 			return 0;
 		udelay(1);
diff --git a/src/southbridge/amd/sb700/lpc.c b/src/southbridge/amd/sb700/lpc.c
index f138d88d72..7b53820e0f 100644
--- a/src/southbridge/amd/sb700/lpc.c
+++ b/src/southbridge/amd/sb700/lpc.c
@@ -93,7 +93,7 @@ void backup_top_of_ram(uint64_t ramtop)
 {
 	u32 dword = (u32) ramtop;
 	int nvram_pos = 0xfc, i;
-	for (i = 0; i<4; i++) {
+	for (i = 0; i < 4; i++) {
 		outb(nvram_pos, BIOSRAM_INDEX);
 		outb((dword >>(8 * i)) & 0xff , BIOSRAM_DATA);
 		nvram_pos++;
diff --git a/src/southbridge/amd/sb700/reset.c b/src/southbridge/amd/sb700/reset.c
index d0cd4a42f0..3c44982e6a 100644
--- a/src/southbridge/amd/sb700/reset.c
+++ b/src/southbridge/amd/sb700/reset.c
@@ -23,7 +23,7 @@
 #define HTIC_BIOSR_Detect	(1<<5)
 
 #if CONFIG_MAX_PHYSICAL_CPUS > 32
-#define NODE_PCI(x, fn)        ((x<32)?(PCI_DEV(CONFIG_CBB,(CONFIG_CDB+x),fn)):(PCI_DEV((CONFIG_CBB-1),(CONFIG_CDB+x-32),fn)))
+#define NODE_PCI(x, fn)        ((x < 32)?(PCI_DEV(CONFIG_CBB,(CONFIG_CDB+x),fn)):(PCI_DEV((CONFIG_CBB-1),(CONFIG_CDB+x-32),fn)))
 #else
 #define NODE_PCI(x, fn)        PCI_DEV(CONFIG_CBB,(CONFIG_CDB+x),fn)
 #endif
diff --git a/src/southbridge/amd/sb800/early_setup.c b/src/southbridge/amd/sb800/early_setup.c
index 070c1f535b..10961596e0 100644
--- a/src/southbridge/amd/sb800/early_setup.c
+++ b/src/southbridge/amd/sb800/early_setup.c
@@ -525,7 +525,7 @@ static void sb800_pmio_por_init(void)
 	byte |= 1 << 0;
 	pmio_write(0xB2, byte);
 
-	for (i=0; i<sizeof(pm_table)/sizeof(struct pm_entry); i++) {
+	for (i = 0; i < sizeof(pm_table)/sizeof(struct pm_entry); i++) {
 		byte = pmio_read(pm_table[i].port);
 		byte &= pm_table[i].mask;
 		byte |= pm_table[i].bit;
@@ -637,7 +637,7 @@ int s3_save_nvram_early(u32 dword, int size, int  nvram_pos)
 	int i;
 	printk(BIOS_DEBUG, "Writing %x of size %d to nvram pos: %d\n", dword, size, nvram_pos);
 
-	for (i = 0; i<size; i++) {
+	for (i = 0; i < size; i++) {
 		outb(nvram_pos, BIOSRAM_INDEX);
 		outb((dword >>(8 * i)) & 0xff , BIOSRAM_DATA);
 		nvram_pos++;
@@ -650,7 +650,7 @@ int s3_load_nvram_early(int size, u32 *old_dword, int nvram_pos)
 {
 	u32 data = *old_dword;
 	int i;
-	for (i = 0; i<size; i++) {
+	for (i = 0; i < size; i++) {
 		outb(nvram_pos, BIOSRAM_INDEX);
 		data &= ~(0xff << (i * 8));
 		data |= inb(BIOSRAM_DATA) << (i *8);
@@ -676,7 +676,7 @@ unsigned long get_top_of_ram(void)
 	int xnvram_pos = 0xfc, xi;
 	if (acpi_get_sleep_type() != 3)
 		return 0;
-	for (xi = 0; xi<4; xi++) {
+	for (xi = 0; xi < 4; xi++) {
 		outb(xnvram_pos, BIOSRAM_INDEX);
 		xdata &= ~(0xff << (xi * 8));
 		xdata |= inb(BIOSRAM_DATA) << (xi *8);
diff --git a/src/southbridge/amd/sb800/enable_usbdebug.c b/src/southbridge/amd/sb800/enable_usbdebug.c
index 7a52e1aa50..3959ea8013 100644
--- a/src/southbridge/amd/sb800/enable_usbdebug.c
+++ b/src/southbridge/amd/sb800/enable_usbdebug.c
@@ -26,9 +26,9 @@
 
 pci_devfn_t pci_ehci_dbg_dev(unsigned int hcd_idx)
 {
-	if (hcd_idx==3)
+	if (hcd_idx == 3)
 		return PCI_DEV(0, 0x16, 2);
-	else if (hcd_idx==2)
+	else if (hcd_idx == 2)
 		return PCI_DEV(0, 0x13, 2);
 	else
 		return PCI_DEV(0, 0x12, 2);
diff --git a/src/southbridge/amd/sb800/hda.c b/src/southbridge/amd/sb800/hda.c
index 2d0852eef4..78e9862266 100644
--- a/src/southbridge/amd/sb800/hda.c
+++ b/src/southbridge/amd/sb800/hda.c
@@ -100,7 +100,7 @@ static int wait_for_ready(void *base)
 	int timeout = 50;
 
 	while (timeout--) {
-		u32 dword=read32(base +  HDA_ICII_REG);
+		u32 dword = read32(base +  HDA_ICII_REG);
 		if (!(dword & HDA_ICII_BUSY))
 			return 0;
 		udelay(1);