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fix epia-m700 compilation, and remove more warnings. 

Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5366 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Stefan Reinauer 2010-04-07 02:30:57 +00:00 committed by Stefan Reinauer
parent 6c214693aa
commit c02c34e886
9 changed files with 15 additions and 13 deletions
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2
src/mainboard/artecgroup/dbe61/mainboard.c
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@ -28,7 +28,7 @@
#include "../../../southbridge/amd/cs5536/cs5536.h"
#include "chip.h"
static void init_gpio()
static void init_gpio(void)
{
msr_t msr;
printk(BIOS_DEBUG, "Checking GPIO module...\n");

2
src/mainboard/intel/eagleheights/acpi_tables.c
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@ -91,7 +91,6 @@ unsigned long acpi_fill_madt(unsigned long current)
{
unsigned int irq_start = 0;
device_t dev = 0;
struct resource* res = NULL;
unsigned char bus_isa;
/* Local Apic */
@ -141,7 +140,6 @@ unsigned long acpi_fill_srat(unsigned long current)
unsigned long write_acpi_tables(unsigned long start)
{
unsigned long current;
int i;
acpi_rsdp_t *rsdp;
acpi_rsdt_t *rsdt;
acpi_hpet_t *hpet;

4
src/mainboard/intel/eagleheights/fadt.c
View File

@ -115,9 +115,9 @@ void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt)
fadt->res3 = 0;
fadt->res4 = 0;
fadt->res5 = 0;
fadt->x_firmware_ctl_l = facs;
fadt->x_firmware_ctl_l = (u32)facs;
fadt->x_firmware_ctl_h = 0;
fadt->x_dsdt_l = dsdt;
fadt->x_dsdt_l = (u32)dsdt;
fadt->x_dsdt_h = 0;
fadt->x_pm1a_evt_blk.space_id = 1;

3
src/mainboard/intel/eagleheights/mainboard.c
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@ -21,10 +21,13 @@
#include <device/device.h>
#include <boot/tables.h>
#include <arch/coreboot_tables.h>
#include "chip.h"
int add_mainboard_resources(struct lb_memory *mem)
{
return 0;
}
struct chip_operations mainboard_ops = {

2
src/mainboard/intel/eagleheights/mptable.c
View File

@ -75,7 +75,7 @@ static void *smp_write_config_table(void *v)
dev = dev_find_slot(0, PCI_DEVFN(0x1F,0));
res = find_resource(dev, RCBA);
if (!res) {
return;
return NULL;
}
rcba = res->base;

2
src/mainboard/intel/xe7501devkit/mptable.c
View File

@ -69,7 +69,7 @@ static void xe7501devkit_register_ioapics(struct mp_config_table *mc)
smp_write_ioapic(mc, IOAPIC_P64H2_1_BUS_B, P64H2_IOAPIC_VERSION, res->base);
}
void xe7501devkit_register_interrupts(struct mp_config_table *mc)
static void xe7501devkit_register_interrupts(struct mp_config_table *mc)
{
// Chipset PCI bus
// Type Trigger | Polarity Bus ID IRQ APIC ID PIN#

1
src/northbridge/via/vx800/vx800.h
View File

@ -21,6 +21,7 @@
#define VX800_H 1
#ifndef __PRE_RAM__
#include <device/device.h>
static inline void vx800_noop(device_t dev)
{
}

10
src/southbridge/intel/i82801cx/i82801cx_lpc.c
View File

@ -23,7 +23,7 @@
#define MAINBOARD_POWER_ON 1
void i82801cx_enable_ioapic( struct device *dev)
static void i82801cx_enable_ioapic( struct device *dev)
{
uint32_t dword;
volatile uint32_t* ioapic_index = (volatile uint32_t*)0xfec00000;
@ -54,7 +54,7 @@ void i82801cx_enable_ioapic( struct device *dev)
}
// This is how interrupts are received from the Super I/O chip
void i82801cx_enable_serial_irqs( struct device *dev)
static void i82801cx_enable_serial_irqs( struct device *dev)
{
// Recognize serial IRQs, continuous mode, frame size 21, 4 clock start frame pulse width
pci_write_config8(dev, SERIRQ_CNTL, (1 << 7)|(1 << 6)|((21 - 17) << 2)|(0<< 0));
@ -69,7 +69,7 @@ void i82801cx_enable_serial_irqs( struct device *dev)
// Return Value: None
// Description: Route all DMA channels to either PCI or LPC.
//
void i82801cx_lpc_route_dma( struct device *dev, uint8_t mask)
static void i82801cx_lpc_route_dma( struct device *dev, uint8_t mask)
{
uint16_t dmaConfig;
int channelIndex;
@ -84,7 +84,7 @@ void i82801cx_lpc_route_dma( struct device *dev, uint8_t mask)
pci_write_config16(dev, PCI_DMA_CFG, dmaConfig);
}
void i82801cx_rtc_init(struct device *dev)
static void i82801cx_rtc_init(struct device *dev)
{
uint32_t dword;
int rtc_failed;
@ -116,7 +116,7 @@ void i82801cx_rtc_init(struct device *dev)
}
void i82801cx_1f0_misc(struct device *dev)
static void i82801cx_1f0_misc(struct device *dev)
{
// Prevent LPC disabling, enable parity errors, and SERR# (System Error)
pci_write_config16(dev, PCI_COMMAND, 0x014f);

2
src/superio/smsc/lpc47b272/superio.c
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@ -45,7 +45,7 @@ static void lpc47b272_init(device_t dev);
static void pnp_enter_conf_state(device_t dev);
static void pnp_exit_conf_state(device_t dev);
static void dump_pnp_device(device_t dev);
//static void dump_pnp_device(device_t dev);
struct chip_operations superio_smsc_lpc47b272_ops = {
CHIP_NAME("SMSC LPC47B272 Super I/O")