mb/google/brya: Introduce new baseboard brask
This patch initiates the brask setting which includes the gpio and device tree setting. BUG=b:191472401 BRANCH=None TEST=build pass Change-Id: I1bb42c7bb2492402de0810bc4ab2e8d8c0e2392b Signed-off-by: Zhuohao Lee <zhuohao@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56388 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
This commit is contained in:
Zhuohao Lee
Paul Fagerburg
parent
c7fd6f2f47
commit
c0308eb860
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@ -1,17 +1,27 @@
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config BOARD_GOOGLE_BASEBOARD_BRYA
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def_bool n
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select ROMSTAGE_SPD_CBFS
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select SYSTEM_TYPE_LAPTOP
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config BOARD_GOOGLE_BASEBOARD_BRASK
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def_bool n
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if BOARD_GOOGLE_BASEBOARD_BRYA || BOARD_GOOGLE_BASEBOARD_BRASK
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config BOARD_GOOGLE_BRYA_COMMON
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def_bool y
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select BOARD_ROMSIZE_KB_32768
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select DRIVERS_GENERIC_MAX98357A
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select DRIVERS_I2C_GENERIC
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select DRIVERS_I2C_HID
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select DRIVERS_GENERIC_MAX98357A
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select DRIVERS_I2C_SX9324
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select DRIVERS_INTEL_DPTF
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select DRIVERS_INTEL_PMC
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select DRIVERS_INTEL_SOUNDWIRE
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select DRIVERS_INTEL_USB4_RETIMER
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select DRIVERS_SPI_ACPI
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select DRIVERS_SOUNDWIRE_ALC5682
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select DRIVERS_SOUNDWIRE_MAX98373
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select DRIVERS_SPI_ACPI
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select DRIVERS_WIFI_GENERIC
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select EC_GOOGLE_CHROMEEC
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select EC_GOOGLE_CHROMEEC_ACPI_MEMMAP
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@ -23,7 +33,6 @@ config BOARD_GOOGLE_BASEBOARD_BRYA
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select GOOGLE_SMBIOS_MAINBOARD_VERSION
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select HAVE_ACPI_RESUME
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select HAVE_ACPI_TABLES
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select HAVE_SPD_IN_CBFS
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select INTEL_LPSS_UART_FOR_CONSOLE
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select MAINBOARD_HAS_CHROMEOS
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select MAINBOARD_HAS_I2C_TPM_CR50
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@ -31,13 +40,11 @@ config BOARD_GOOGLE_BASEBOARD_BRYA
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select SOC_INTEL_ALDERLAKE
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select SOC_INTEL_COMMON_BLOCK_PCIE_RTD3
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select SOC_INTEL_CSE_LITE_SKU
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select SYSTEM_TYPE_LAPTOP
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if BOARD_GOOGLE_BASEBOARD_BRYA
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config BASEBOARD_DIR
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string
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default "brya" if BOARD_GOOGLE_BASEBOARD_BRYA
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default "brask" if BOARD_GOOGLE_BASEBOARD_BRASK
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config CHROMEOS
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select CHROMEOS_DRAM_PART_NUMBER_IN_CBI
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@ -69,9 +76,11 @@ config MAINBOARD_DIR
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config MAINBOARD_FAMILY
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string
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default "Google_Brya" if BOARD_GOOGLE_BASEBOARD_BRYA
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default "Google_Brask" if BOARD_GOOGLE_BASEBOARD_BRASK
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config MAINBOARD_PART_NUMBER
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default "Brya" if BOARD_GOOGLE_BRYA0
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default "Brask" if BOARD_GOOGLE_BRASK
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default "Primus" if BOARD_GOOGLE_PRIMUS
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default "Gimble" if BOARD_GOOGLE_GIMBLE
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default "Redrix" if BOARD_GOOGLE_REDRIX
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@ -81,6 +90,7 @@ config MAINBOARD_PART_NUMBER
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config VARIANT_DIR
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default "brya0" if BOARD_GOOGLE_BRYA0
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default "brask" if BOARD_GOOGLE_BRASK
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default "primus" if BOARD_GOOGLE_PRIMUS
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default "gimble" if BOARD_GOOGLE_GIMBLE
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default "redrix" if BOARD_GOOGLE_REDRIX
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@ -96,4 +106,8 @@ config UART_FOR_CONSOLE
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int
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default 0
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endif # BOARD_GOOGLE_BASEBOARD_BRYA
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config ROMSTAGE_SPD_CBFS
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def_bool n
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select HAVE_SPD_IN_CBFS
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endif # BOARD_GOOGLE_BASEBOARD_BRYA || BOARD_GOOGLE_BASEBOARD_BRASK
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@ -6,6 +6,12 @@ config BOARD_GOOGLE_BRYA0
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select DRIVERS_INTEL_MIPI_CAMERA
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select SOC_INTEL_COMMON_BLOCK_IPU
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config BOARD_GOOGLE_BRASK
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bool "Brask"
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select BOARD_GOOGLE_BASEBOARD_BRASK
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select ADL_ENABLE_USB4_PCIE_RESOURCES
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select SOC_INTEL_CRASHLOG
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config BOARD_GOOGLE_PRIMUS
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bool "-> Primus"
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select BOARD_GOOGLE_BASEBOARD_BRYA
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@ -3,7 +3,7 @@ bootblock-y += bootblock.c
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verstage-$(CONFIG_CHROMEOS) += chromeos.c
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romstage-$(CONFIG_CHROMEOS) += chromeos.c
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romstage-y += romstage.c
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romstage-$(CONFIG_ROMSTAGE_SPD_CBFS) += romstage_spd_cbfs.c
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ramstage-$(CONFIG_CHROMEOS) += chromeos.c
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ramstage-y += mainboard.c
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@ -15,7 +15,8 @@ BASEBOARD_DIR:=$(call strip_quotes,$(CONFIG_BASEBOARD_DIR))
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subdirs-y += variants/baseboard/$(BASEBOARD_DIR)
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subdirs-y += variants/$(VARIANT_DIR)
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subdirs-y += variants/$(VARIANT_DIR)/memory
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subdirs-y += spd
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subdirs-$(CONFIG_ROMSTAGE_SPD_CBFS) += spd
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CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/variants/baseboard/include
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CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/variants/baseboard/$(BASEBOARD_DIR)/include
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CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/variants/$(VARIANT_DIR)/include
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@ -0,0 +1,3 @@
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bootblock-y += gpio.c
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ramstage-y += gpio.c
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@ -0,0 +1,150 @@
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chip soc/intel/alderlake
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device cpu_cluster 0 on
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device lapic 0 on end
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end
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# GPE configuration
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register "pmc_gpe0_dw0" = "GPP_A"
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register "pmc_gpe0_dw1" = "GPP_E"
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register "pmc_gpe0_dw2" = "GPP_F"
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# EC host command ranges are in 0x800-0x8ff & 0x200-0x20f
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register "gen1_dec" = "0x00fc0801"
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register "gen2_dec" = "0x000c0201"
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# EC memory map range is 0x900-0x9ff
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register "gen3_dec" = "0x00fc0901"
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# S0ix enable
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register "s0ix_enable" = "1"
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# DPTF enable
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register "dptf_enable" = "1"
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# Enable heci communication
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register "HeciEnabled" = "1"
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# This disabled autonomous GPIO power management, otherwise
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# old cr50 FW only supports short pulses; need to clarify
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# the minimum PCH IRQ pulse width with Intel, b/180111628
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register "gpio_override_pm" = "1"
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register "gpio_pm[COMM_0]" = "0"
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register "gpio_pm[COMM_1]" = "0"
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register "gpio_pm[COMM_2]" = "0"
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register "gpio_pm[COMM_3]" = "0"
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register "gpio_pm[COMM_4]" = "0"
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register "gpio_pm[COMM_5]" = "0"
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# Enable CNVi BT
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register "CnviBtCore" = "true"
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register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC0)" # USB2_C0
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register "usb2_ports[1]" = "USB2_PORT_TYPE_C(OC1)" # USB2_C1
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register "usb2_ports[2]" = "USB2_PORT_TYPE_C(OC2)" # USB2_C2
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register "usb2_ports[4]" = "USB2_PORT_MID(OC_SKIP)" # NFC
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register "usb2_ports[5]" = "USB2_PORT_MID(OC_SKIP)" # Type-A Port A3
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register "usb2_ports[6]" = "USB2_PORT_MID(OC_SKIP)" # Type-A Port A2
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register "usb2_ports[7]" = "USB2_PORT_MID(OC_SKIP)" # Type-A Port A1
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register "usb2_ports[8]" = "USB2_PORT_MID(OC_SKIP)" # Type-A Port A0
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register "usb2_ports[9]" = "USB2_PORT_MID(OC_SKIP)" # M.2 Bluetooth
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register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type-A port A0
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register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type-A port A1(DCI)
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register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type-A port A2
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register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type-A port A3
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register "tcss_ports[0]" = "TCSS_PORT_DEFAULT(OC0)"
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register "tcss_ports[1]" = "TCSS_PORT_DEFAULT(OC1)"
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register "tcss_ports[2]" = "TCSS_PORT_DEFAULT(OC2)"
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register "SerialIoI2cMode" = "{
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[PchSerialIoIndexI2C0] = PchSerialIoPci,
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[PchSerialIoIndexI2C1] = PchSerialIoDisabled,
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[PchSerialIoIndexI2C2] = PchSerialIoDisabled,
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[PchSerialIoIndexI2C3] = PchSerialIoPci,
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[PchSerialIoIndexI2C4] = PchSerialIoDisabled,
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[PchSerialIoIndexI2C5] = PchSerialIoDisabled,
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}"
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register "SerialIoGSpiMode" = "{
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[PchSerialIoIndexGSPI0] = PchSerialIoDisabled,
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[PchSerialIoIndexGSPI1] = PchSerialIoPci,
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}"
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register "SerialIoUartMode" = "{
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[PchSerialIoIndexUART0] = PchSerialIoPci,
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[PchSerialIoIndexUART1] = PchSerialIoDisabled,
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[PchSerialIoIndexUART2] = PchSerialIoDisabled,
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}"
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# HD Audio
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register "PchHdaDspEnable" = "1"
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register "PchHdaIDispLinkTmode" = "HDA_TMODE_8T"
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register "PchHdaIDispLinkFrequency" = "HDA_LINKFREQ_96MHZ"
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register "PchHdaIDispCodecEnable" = "1"
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# Intel Common SoC Config
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#+-------------------+---------------------------+
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#| Field | Value |
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#+-------------------+---------------------------+
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#| chipset_lockdown | CHIPSET_LOCKDOWN_COREBOOT |
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#| GSPI1 | Fingerprint MCU |
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#| I2C0 | Audio |
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#| I2C3 | cr50 TPM. Early init is |
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#| | required to set up a BAR |
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#| | for TPM communication |
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#+-------------------+---------------------------+
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register "common_soc_config.chipset_lockdown" = "CHIPSET_LOCKDOWN_COREBOOT"
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register "common_soc_config" = "{
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.i2c[0] = {
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.speed = I2C_SPEED_FAST,
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},
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.i2c[3] = {
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.early_init = 1,
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.speed = I2C_SPEED_FAST,
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},
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}"
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device domain 0 on
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device ref igpu on end
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device ref dtt on end
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device ref tbt_pcie_rp0 on end
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device ref tbt_pcie_rp1 on end
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device ref tbt_pcie_rp2 on end
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device ref tcss_xhci on end
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device ref tcss_dma0 on end
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device ref tcss_dma1 on end
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device ref xhci on end
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device ref shared_sram on end
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device ref cnvi_wifi on
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chip drivers/wifi/generic
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register "wake" = "GPE0_PME_B0"
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device generic 0 on end
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end
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end
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device ref i2c3 on
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chip drivers/i2c/tpm
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register "hid" = ""GOOG0005""
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register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_A13_IRQ)"
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device i2c 50 on end
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end
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end
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device ref heci1 on end
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device ref sata on end
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device ref pcie_rp8 on
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# Enable SD Card PCIE 8 using clk 3
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register "pch_pcie_rp[PCH_RP(8)]" = "{
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.clk_src = 3,
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.clk_req = 3,
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.flags = PCIE_RP_HOTPLUG | PCIE_RP_LTR | PCIE_RP_AER,
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}"
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end #PCIE8 SD card
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device ref uart0 on end
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device ref gspi1 on end
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device ref pch_espi on
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chip ec/google/chromeec
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device pnp 0c09.0 on end
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end
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end
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device ref hda on end
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end
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end
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@ -0,0 +1,424 @@
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/* SPDX-License-Identifier: GPL-2.0-or-later */
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#include <baseboard/gpio.h>
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#include <baseboard/variants.h>
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#include <commonlib/helpers.h>
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#include <soc/gpio.h>
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#include <vendorcode/google/chromeos/chromeos.h>
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/* Pad configuration in ramstage */
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static const struct pad_config gpio_table[] = {
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/* A0 thru A5, A9 and A10 come configured out of reset, do not touch */
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/* A0 : ESPI_IO0 ==> ESPI_IO_0 */
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/* A1 : ESPI_IO1 ==> ESPI_IO_1 */
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/* A2 : ESPI_IO2 ==> ESPI_IO_2 */
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/* A3 : ESPI_IO3 ==> ESPI_IO_3 */
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/* A4 : ESPI_CS# ==> ESPI_CS_L */
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/* A5 : ESPI_ALERT0# ==> TP78 */
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PAD_NC(GPP_A5, NONE),
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/* A6 : ESPI_ALERT1# ==> TP88 */
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PAD_NC(GPP_A6, NONE),
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/* A7 : SRCCLK_OE7# ==> NC */
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PAD_NC(GPP_A7, NONE),
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/* A8 : SRCCLKREQ7# ==> CLKREQ_7 */
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PAD_NC(GPP_A8, NONE),
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/* A9 : ESPI_CLK ==> ESPI_CLK */
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/* A10 : ESPI_RESET# ==> ESPI_PCH_RST_EC_L */
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/* A11 : PMC_I2C_SDA ==> NC */
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PAD_NC(GPP_A11, NONE),
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/* A12 : SATAXPCIE1 ==> CLKREQ_9B */
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PAD_NC(GPP_A12, NONE),
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/* A13 : PMC_I2C_SCL ==> GSC_PCH_INT_ODL */
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PAD_CFG_GPI_APIC(GPP_A13, NONE, PLTRST, LEVEL, INVERT),
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/* A14 : USB_OC1# ==> USB_C1_OC_ODL */
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PAD_CFG_NF(GPP_A14, NONE, DEEP, NF1),
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/* A15 : USB_OC2# ==> USB_C2_OC_ODL */
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PAD_CFG_NF(GPP_A15, NONE, DEEP, NF1),
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/* A16 : USB_OC3# ==> USB_A0_OC_ODL */
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PAD_CFG_NF(GPP_A16, NONE, DEEP, NF1),
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/* A17 : DISP_MISCC ==> NC */
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PAD_NC(GPP_A17, NONE),
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/* A18 : DDSP_HPDB ==> HDMI_HPD */
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PAD_CFG_NF(GPP_A18, NONE, DEEP, NF1),
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/* A19 : DDSP_HPD1 ==> USB_C2_AUX_DC_P */
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PAD_CFG_NF(GPP_A19, NONE, DEEP, NF6),
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/* A20 : DDSP_HPD2 ==> USB_C2_AUX_DC_N */
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PAD_CFG_NF(GPP_A20, NONE, DEEP, NF6),
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/* A21 : DDPC_CTRCLK ==> USB_C1_AUX_DC_P */
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PAD_CFG_NF(GPP_A21, NONE, DEEP, NF6),
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/* A22 : DDPC_CTRLDATA ==> USB_C1_AUX_DC_N */
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PAD_CFG_NF(GPP_A22, NONE, DEEP, NF6),
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/* A23 : ESPI_CS1# ==> AUD_HP_INT_L */
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PAD_CFG_GPI_INT(GPP_A23, NONE, PLTRST, EDGE_BOTH),
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/* B0 : SOC_VID0 */
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PAD_CFG_NF(GPP_B0, NONE, DEEP, NF1),
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/* B1 : SOC_VID1 */
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PAD_CFG_NF(GPP_B1, NONE, DEEP, NF1),
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/* B2 : VRALERT# ==> M2_SSD_PLA_L */
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PAD_CFG_GPO(GPP_B2, 1, PLTRST),
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/* B3 : PROC_GP2 ==> NC */
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PAD_NC(GPP_B3, NONE),
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/* B4 : PROC_GP3 ==> SSD_PERST_L */
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PAD_CFG_GPO(GPP_B4, 1, DEEP),
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/* B5 : ISH_I2C0_SDA ==> NC */
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PAD_NC(GPP_B5, NONE),
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/* B6 : ISH_I2C0_SCL ==> NC */
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PAD_NC(GPP_B6, NONE),
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/* B7 : ISH_12C1_SDA ==> PCH_I2C_TPM_SDA */
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PAD_CFG_NF(GPP_B7, NONE, DEEP, NF2),
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/* B8 : ISH_I2C1_SCL ==> PCH_I2C_TPM_SCL */
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PAD_CFG_NF(GPP_B8, NONE, DEEP, NF2),
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/* B9 : NC */
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PAD_NC(GPP_B9, NONE),
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/* B10 : NC */
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PAD_NC(GPP_B10, NONE),
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/* B11 : PMCALERT# ==> EN_PP3300_WLAN */
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PAD_CFG_GPO(GPP_B11, 1, DEEP),
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/* B12 : SLP_S0# ==> SLP_S0_L */
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PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1),
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/* B13 : PLTRST# ==> PLT_RST_L */
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PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1),
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/* B14 : SPKR ==> GPP_B14_STRAP */
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PAD_NC(GPP_B14, NONE),
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/* B15 : TIME_SYNC0 ==> TP159 */
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PAD_NC(GPP_B15, NONE),
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/* B16 : I2C5_SDA ==> NC */
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PAD_NC(GPP_B16, NONE),
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/* B17 : I2C5_SCL ==> NC */
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PAD_NC(GPP_B17, NONE),
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/* B18 : ADR_COMPLETE ==> GPP_B18_STRAP */
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PAD_NC(GPP_B18, NONE),
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/* B19 : NC */
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PAD_NC(GPP_B19, NONE),
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/* B20 : NC */
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PAD_NC(GPP_B20, NONE),
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||||
/* B21 : NC */
|
||||
PAD_NC(GPP_B21, NONE),
|
||||
/* B22 : NC */
|
||||
PAD_NC(GPP_B22, NONE),
|
||||
/* B23 : SML1ALERT# ==> PCHHOT_ODL_STRAP */
|
||||
PAD_NC(GPP_B23, NONE),
|
||||
|
||||
/* C0 : SMBCLK ==> DDR_SMB_CLK */
|
||||
PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1),
|
||||
/* C1 : SMBDATA ==> DDR_SMB_DATA */
|
||||
PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1),
|
||||
/* C2 : SMBALERT# ==> GPP_C2_STRAP */
|
||||
PAD_NC(GPP_C2, NONE),
|
||||
/* C3 : SML0CLK ==> USB_C0_AUX_DC_P */
|
||||
PAD_NC(GPP_C3, NONE),
|
||||
/* C4 : SML0DATA ==> USB_C0_AUX_DC_N */
|
||||
PAD_NC(GPP_C4, NONE),
|
||||
/* C5 : SML0ALERT# ==> GPP_C5_BOOT_STRAP0 */
|
||||
PAD_NC(GPP_C5, NONE),
|
||||
/* C6 : SML1CLK ==> NC */
|
||||
PAD_NC(GPP_C6, NONE),
|
||||
/* C7 : SML1DATA ==> NC */
|
||||
PAD_NC(GPP_C7, NONE),
|
||||
|
||||
/* D0 : ISH_GP0 ==> PCH_FP_BOOT0 */
|
||||
PAD_NC(GPP_D0, NONE),
|
||||
/* D1 : ISH_GP1 ==> FP_RST_ODL */
|
||||
PAD_CFG_GPO(GPP_D1, 1, DEEP),
|
||||
/* D2 : ISH_GP2 ==> EN_FP_PWR */
|
||||
PAD_CFG_GPO(GPP_D2, 1, DEEP),
|
||||
/* D3 : ISH_GP3 ==> EN_NFC_PWR */
|
||||
PAD_CFG_GPO(GPP_D3, 1, DEEP),
|
||||
/* D4 : IMGCLKOUT0 ==> BT_DISABLE_L */
|
||||
PAD_CFG_GPO(GPP_D4, 1, DEEP),
|
||||
/* D5 : SRCCLKREQ0# ==> SSD_CLKREQ_ODL */
|
||||
PAD_CFG_NF(GPP_D5, NONE, DEEP, NF1),
|
||||
/* D6 : SRCCLKREQ1# ==> CLKREQ_1 */
|
||||
PAD_NC(GPP_D6, NONE),
|
||||
/* D7 : SRCCLKREQ2# ==> WLAN_CLKREQ_ODL */
|
||||
PAD_CFG_NF(GPP_D7, NONE, DEEP, NF1),
|
||||
/* D8 : SRCCLKREQ3# ==> SD_CLKREQ_ODL */
|
||||
PAD_CFG_NF(GPP_D8, NONE, DEEP, NF1),
|
||||
/* D9 : ISH_SPI_CS# ==> USB_C2_LSX_TX */
|
||||
PAD_CFG_NF(GPP_D9, NONE, DEEP, NF4),
|
||||
/* D10 : ISH_SPI_CLK ==> USB_C2_LSX_RX_STRAP */
|
||||
PAD_CFG_NF(GPP_D10, NONE, DEEP, NF4),
|
||||
/* D11 : ISH_SPI_MISO ==> EN_PP3300_SSD */
|
||||
PAD_CFG_GPO(GPP_D11, 1, DEEP),
|
||||
/* D12 : ISH_SPI_MOSI ==> GPP_D12_STRAP */
|
||||
PAD_NC(GPP_D12, NONE),
|
||||
/* D13 : ISH_UART0_RXD ==> TP97 */
|
||||
PAD_NC(GPP_D13, NONE),
|
||||
/* D14 : ISH_UART0_TXD ==> TP93 */
|
||||
PAD_NC(GPP_D14, NONE),
|
||||
/* D15 : ISH_UART0_RTS# ==> NC */
|
||||
PAD_NC(GPP_D15, NONE),
|
||||
/* D16 : ISH_UART0_CTS# ==> NC */
|
||||
PAD_NC(GPP_D16, NONE),
|
||||
/* D17 : UART1_RXD ==> SD_PE_PRSNT_L */
|
||||
PAD_CFG_GPI(GPP_D17, NONE, DEEP),
|
||||
/* D18 : UART1_TXD ==> SD_PE_RST_L */
|
||||
PAD_CFG_GPO(GPP_D18, 1, DEEP),
|
||||
/* D19 : I2S_MCLK1_OUT ==> I2S_MCLK_R */
|
||||
PAD_CFG_NF(GPP_D19, NONE, DEEP, NF1),
|
||||
|
||||
/* E0 : SATAXPCIE0 ==> CLKREQ_9 */
|
||||
PAD_NC(GPP_E0, NONE),
|
||||
/* E1 : THC0_SPI1_IO2 ==> NC */
|
||||
PAD_NC(GPP_E1, NONE),
|
||||
/* E2 : THC0_SPI1_IO3 ==> NC */
|
||||
PAD_NC(GPP_E2, NONE),
|
||||
/* E3 : PROC_GP0 ==> TP94644 */
|
||||
PAD_NC(GPP_E3, NONE),
|
||||
/* E4 : SATA_DEVSLP0 ==> USB4_BB_RT_FORCE_PWR */
|
||||
PAD_CFG_GPO(GPP_E4, 1, DEEP),
|
||||
/* E5 : SATA_DEVSLP1 ==> NC */
|
||||
PAD_NC(GPP_E5, NONE),
|
||||
/* E6 : THC0_SPI1_RST# ==> GPPE6_STRAP */
|
||||
PAD_NC(GPP_E6, NONE),
|
||||
/* E7 : PROC_GP1 ==> TP94643 */
|
||||
PAD_NC(GPP_E7, NONE),
|
||||
/* E8 : SLP_DRAM# ==> WIFI_DISABLE_L */
|
||||
PAD_CFG_GPO(GPP_E8, 1, DEEP),
|
||||
/* E9 : USB_OC0# ==> USB_C0_OC_ODL */
|
||||
PAD_CFG_NF(GPP_E9, NONE, DEEP, NF1),
|
||||
/* E10 : THC0_SPI1_CS# ==> NC */
|
||||
PAD_NC(GPP_E10, NONE),
|
||||
/* E11 : THC0_SPI1_CLK ==> NC */
|
||||
PAD_NC(GPP_E11, NONE),
|
||||
/* E12 : THC0_SPI1_IO1 ==> NC */
|
||||
PAD_NC(GPP_E12, NONE),
|
||||
/* E13 : THC0_SPI1_IO2 ==> NC */
|
||||
PAD_NC(GPP_E13, NONE),
|
||||
/* E14 : DDSP_HPDA ==> SOC_DP_HPD */
|
||||
PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1),
|
||||
/* E15 : RSVD_TP ==> PCH_WP_OD */
|
||||
PAD_CFG_GPI_GPIO_DRIVER(GPP_E15, NONE, DEEP),
|
||||
/* E16 : RSVD_TP ==> CLKREQ_8 */
|
||||
PAD_NC(GPP_E16, NONE),
|
||||
/* E17 : THC0_SPI1_INT# ==> TP102 */
|
||||
PAD_NC(GPP_E17, NONE),
|
||||
/* E18 : DDP1_CTRLCLK ==> USB_C0_LSX_TX */
|
||||
PAD_CFG_NF(GPP_E18, NONE, DEEP, NF4),
|
||||
/* E19 : DDP1_CTRLDATA ==> USB0_C0_LSX_RX_STRAP */
|
||||
PAD_CFG_NF(GPP_E19, NONE, DEEP, NF4),
|
||||
/* E20 : DDP2_CTRLCLK ==> USB_C1_LSX_TX */
|
||||
PAD_CFG_NF(GPP_E20, NONE, DEEP, NF4),
|
||||
/* E21 : DDP2_CTRLDATA ==> USB_C1_LSX_RX_STRAP */
|
||||
PAD_CFG_NF(GPP_E21, NONE, DEEP, NF4),
|
||||
/* E22 : DDPA_CTRLCLK ==> DDIA_DP_CTRLCLK */
|
||||
PAD_CFG_NF(GPP_E22, NONE, DEEP, NF1),
|
||||
/* E23 : DDPA_CTRLDATA ==> DDIA_DP_CTRLDATA */
|
||||
PAD_CFG_NF(GPP_E23, NONE, DEEP, NF1),
|
||||
|
||||
/* F0 : CNV_BRI_DT ==> CNV_BRI_DT_STRAP */
|
||||
PAD_CFG_NF(GPP_F0, NONE, DEEP, NF1),
|
||||
/* F1 : CNV_BRI_RSP ==> CNV_BRI_RSP */
|
||||
PAD_CFG_NF(GPP_F1, UP_20K, DEEP, NF1),
|
||||
/* F2 : CNV_RGI_DT ==> CNV_RGI_DT_STRAP */
|
||||
PAD_CFG_NF(GPP_F2, NONE, DEEP, NF1),
|
||||
/* F3 : CNV_RGI_RSP ==> CNV_RGI_RSP */
|
||||
PAD_CFG_NF(GPP_F3, UP_20K, DEEP, NF1),
|
||||
/* F4 : CNV_RF_RESET# ==> CNV_RF_RST_L */
|
||||
PAD_CFG_NF(GPP_F4, NONE, DEEP, NF1),
|
||||
/* F5 : MODEM_CLKREQ ==> CNV_CLKREQ0 */
|
||||
PAD_CFG_NF(GPP_F5, NONE, DEEP, NF3),
|
||||
/* F6 : CNV_PA_BLANKING ==> WWAN_WLAN_COEX3 */
|
||||
PAD_CFG_NF(GPP_F6, NONE, DEEP, NF1),
|
||||
/* F7 : GPPF7_STRAP */
|
||||
PAD_NC(GPP_F7, NONE),
|
||||
/* F8 : NC */
|
||||
PAD_NC(GPP_F8, NONE),
|
||||
/* F9 : BOOTMPC ==> SLP_S0_GATE_R */
|
||||
PAD_CFG_GPO(GPP_F9, 1, PLTRST),
|
||||
/* F10 : GPPF10_STRAP */
|
||||
PAD_NC(GPP_F10, DN_20K),
|
||||
/* F11 : THC1_SPI2_CLK ==> GSPI_PCH_CLK_FPMCU_R */
|
||||
PAD_CFG_NF(GPP_F11, NONE, DEEP, NF4),
|
||||
/* F12 : GSXDOUT ==> GSPI_PCH_DO_FPMCU_DI_R */
|
||||
PAD_CFG_NF(GPP_F12, NONE, DEEP, NF4),
|
||||
/* F13 : GSXDOUT ==> GSPI_PCH_DI_FPMCU_DO */
|
||||
PAD_CFG_NF(GPP_F13, NONE, DEEP, NF4),
|
||||
/* F14 : GSXDIN ==> NC */
|
||||
PAD_NC(GPP_F14, NONE),
|
||||
/* F15 : GSXSRESET# ==> FPMCU_INT_L */
|
||||
PAD_CFG_GPI_IRQ_WAKE(GPP_F15, NONE, DEEP, LEVEL, INVERT),
|
||||
/* F16 : GSXCLK ==> GSPI_PCH_CS_FPMCU_R_L */
|
||||
PAD_CFG_NF(GPP_F16, NONE, DEEP, NF4),
|
||||
/* F17 : THC1_SPI2_RST# ==> EC_PCH_INT_ODL */
|
||||
PAD_CFG_GPI_IRQ_WAKE(GPP_F17, NONE, DEEP, LEVEL, INVERT),
|
||||
/* F18 : THC1_SPI2_INT# ==> EC_IN_RW_OD */
|
||||
PAD_CFG_GPI(GPP_F18, NONE, DEEP),
|
||||
/* F19 : SRCCLKREQ6# ==> LAN_CLKREQ_ODL */
|
||||
PAD_CFG_NF(GPP_F19, NONE, DEEP, NF1),
|
||||
/* F20 : EXT_PWR_GATE# ==> TP94669 */
|
||||
PAD_NC(GPP_F20, NONE),
|
||||
/* F21 : EXT_PWR_GATE2# ==> TP94579 */
|
||||
PAD_NC(GPP_F21, NONE),
|
||||
/* F22 : VNN_CTRL ==> TP153 */
|
||||
PAD_NC(GPP_F22, NONE),
|
||||
/* F23 : V1P05_CTRL ==> TP154 */
|
||||
PAD_NC(GPP_F23, NONE),
|
||||
|
||||
/* H0 : GPPH0_BOOT_STRAP1 */
|
||||
PAD_NC(GPP_H0, NONE),
|
||||
/* H1 : GPPH1_BOOT_STRAP2 */
|
||||
PAD_NC(GPP_H1, NONE),
|
||||
/* H2 : GPPH2_BOOT_STRAP3 */
|
||||
PAD_NC(GPP_H2, NONE),
|
||||
/* H3 : SX_EXIT_HOLDOFF# ==> WLAN_PCIE_WAKE_ODL */
|
||||
PAD_CFG_GPI(GPP_H3, NONE, DEEP),
|
||||
/* H4 : I2C0_SDA ==> PCH_I2C_AUD_SDA */
|
||||
PAD_CFG_NF(GPP_H4, NONE, DEEP, NF1),
|
||||
/* H5 : I2C0_SCL ==> PCH_I2C_AUD_SCL */
|
||||
PAD_CFG_NF(GPP_H5, NONE, DEEP, NF1),
|
||||
/* H6 : I2C1_SDA ==> NC */
|
||||
PAD_NC(GPP_H6, NONE),
|
||||
/* H7 : I2C1_SCL ==> NC */
|
||||
PAD_NC(GPP_H7, NONE),
|
||||
/* H8 : I2C4_SDA ==> WWAN_WLAN_COEX1 */
|
||||
PAD_CFG_NF(GPP_H8, NONE, DEEP, NF2),
|
||||
/* H9 : I2C4_SCL ==> WWAN_WLAN_COEX2 */
|
||||
PAD_CFG_NF(GPP_H9, NONE, DEEP, NF2),
|
||||
/* H10 : UART0_RXD ==> UART_PCH_RX_DBG_TX */
|
||||
PAD_CFG_NF(GPP_H10, NONE, DEEP, NF2),
|
||||
/* H11 : UART0_TXD ==> UART_PCH_TX_DBG_RX */
|
||||
PAD_CFG_NF(GPP_H11, NONE, DEEP, NF2),
|
||||
/* H12 : I2C7_SDA ==> SD_PE_WAKE_ODL */
|
||||
PAD_CFG_GPI(GPP_H12, NONE, DEEP),
|
||||
/* H13 : I2C7_SCL ==> EN_PP3300_SD */
|
||||
PAD_CFG_GPO(GPP_H13, 1, DEEP),
|
||||
/* H14 : NC */
|
||||
PAD_NC(GPP_H14, NONE),
|
||||
/* H15 : DDPB_CTRLCLK ==> DDIB_HDMI_CTRLCLK */
|
||||
PAD_CFG_NF(GPP_H15, NONE, DEEP, NF1),
|
||||
/* H16 : NC */
|
||||
PAD_NC(GPP_H16, NONE),
|
||||
/* H17 : DDPB_CTRLDATA ==> DDIB_HDMI_CTRLDATA */
|
||||
PAD_CFG_NF(GPP_H17, NONE, DEEP, NF1),
|
||||
/* H18 : PROC_C10_GATE# ==> CPU_C10_GATE_L */
|
||||
PAD_CFG_NF(GPP_H18, NONE, DEEP, NF1),
|
||||
/* H19 : SRCCLKREQ4# ==> CLKREQ_4 */
|
||||
PAD_NC(GPP_H19, NONE),
|
||||
/* H20 : IMGCLKOUT1 ==> WLAN_PERST_L */
|
||||
PAD_CFG_GPO(GPP_H20, 1, DEEP),
|
||||
/* H21 : IMGCLKOUT2 ==> TP94574 */
|
||||
PAD_NC(GPP_H21, NONE),
|
||||
/* H22 : IMGCLKOUT3 ==> LAN_PE_ISOLATE_ODL */
|
||||
PAD_CFG_GPO(GPP_H22, 1, DEEP),
|
||||
/* H23 : SRCCLKREQ5# ==> M2_SSD_PLN_L */
|
||||
PAD_CFG_GPO(GPP_H23, 1, PLTRST),
|
||||
|
||||
/* R0 : HDA_BCLK ==> I2S_HP_SCLK_R */
|
||||
PAD_CFG_NF(GPP_R0, NONE, DEEP, NF2),
|
||||
/* R1 : HDA_SYNC ==> I2S_HP_SFRM_R */
|
||||
PAD_CFG_NF(GPP_R1, NONE, DEEP, NF2),
|
||||
/* R2 : HDA_SDO ==> I2S_PCH_TX_HP_RX_STRAP */
|
||||
PAD_CFG_NF(GPP_R2, DN_20K, DEEP, NF2),
|
||||
/* R3 : HDA_SDIO ==> I2S_PCH_RX_HP_TX */
|
||||
PAD_CFG_NF(GPP_R3, NONE, DEEP, NF2),
|
||||
/* R4 : HDA_RST# ==> DMIC_CLK0_R */
|
||||
PAD_CFG_NF(GPP_R4, NONE, DEEP, NF3),
|
||||
/* R5 : HDA_SDI1 ==> DMIC_DATA0_R */
|
||||
PAD_CFG_NF(GPP_R5, NONE, DEEP, NF3),
|
||||
/* R6 : I2S2_TXD ==> DMIC_CLK1_R */
|
||||
PAD_CFG_NF(GPP_R6, NONE, DEEP, NF3),
|
||||
/* R7 : I2S2_RXD ==> DMIC_DATA1_R */
|
||||
PAD_CFG_NF(GPP_R7, NONE, DEEP, NF3),
|
||||
|
||||
/* S0 : SNDW0_CLK ==> NC */
|
||||
PAD_NC(GPP_S0, NONE),
|
||||
/* S1 : SNDW0_DATA ==> NC */
|
||||
PAD_NC(GPP_S1, NONE),
|
||||
/* S2 : SNDW1_CLK ==> NC */
|
||||
PAD_NC(GPP_S2, NONE),
|
||||
/* S3 : SNDW1_DATA ==> NC */
|
||||
PAD_NC(GPP_S3, NONE),
|
||||
/* S4 : SNDW2_CLK ==> NC */
|
||||
PAD_NC(GPP_S4, NONE),
|
||||
/* S5 : SNDW2_DATA ==> NC */
|
||||
PAD_NC(GPP_S5, NONE),
|
||||
/* S6 : SNDW3_CLK ==> NC */
|
||||
PAD_NC(GPP_S6, NONE),
|
||||
/* S7 : SNDW3_DATA ==> NC */
|
||||
PAD_NC(GPP_S7, NONE),
|
||||
|
||||
/* GPD0: BATLOW# ==> BATLOW_L */
|
||||
PAD_CFG_NF(GPD0, NONE, DEEP, NF1),
|
||||
/* GPD1: ACPRESENT ==> ACPRESENT */
|
||||
PAD_CFG_NF(GPD1, NONE, DEEP, NF1),
|
||||
/* GPD2 : LAN_WAKE# ==> EC_PCH_WAKE_ODL */
|
||||
PAD_CFG_NF(GPD2, NONE, DEEP, NF1),
|
||||
/* GPD3: PWRBTN# ==> EC_PCH_PWR_BTN_ODL */
|
||||
PAD_CFG_NF(GPD3, NONE, DEEP, NF1),
|
||||
/* GPD4: SLP_S3# ==> SLP_S3_L */
|
||||
PAD_CFG_NF(GPD4, NONE, DEEP, NF1),
|
||||
/* GPD5: SLP_S4# ==> SLP_S4_L */
|
||||
PAD_CFG_NF(GPD5, NONE, DEEP, NF1),
|
||||
/* GPD6: SLP_A# ==> SLP_A_L_CAP_SITE */
|
||||
PAD_CFG_NF(GPD6, NONE, DEEP, NF1),
|
||||
/* GPD7: GPD7_STRAP */
|
||||
PAD_NC(GPD7, NONE),
|
||||
/* GPD8: SUSCLK ==> PCH_SUSCLK */
|
||||
PAD_CFG_NF(GPD8, NONE, DEEP, NF1),
|
||||
/* GPD9: SLP_WLAN# ==> SLP_WLAN_L_CAP_SITE */
|
||||
PAD_CFG_NF(GPD9, NONE, DEEP, NF1),
|
||||
/* GPD10: SLP_S5# ==> SLP_S5_L */
|
||||
PAD_CFG_NF(GPD10, NONE, DEEP, NF1),
|
||||
/* GPD11: LANPHYC ==> TP99 */
|
||||
PAD_NC(GPD11, NONE),
|
||||
};
|
||||
|
||||
/* Early pad configuration in bootblock */
|
||||
static const struct pad_config early_gpio_table[] = {
|
||||
/* A13 : PMC_I2C_SCL ==> GSC_PCH_INT_ODL */
|
||||
PAD_CFG_GPI_APIC(GPP_A13, NONE, PLTRST, LEVEL, INVERT),
|
||||
/* B7 : ISH_12C1_SDA ==> PCH_I2C_TPM_SDA */
|
||||
PAD_CFG_NF(GPP_B7, NONE, DEEP, NF2),
|
||||
/* B8 : ISH_12C1_SCL ==> PCH_I2C_TPM_SCL */
|
||||
PAD_CFG_NF(GPP_B8, NONE, DEEP, NF2),
|
||||
/*
|
||||
* D1 : ISH_GP1 ==> FP_RST_ODL
|
||||
* FP_RST_ODL comes out of reset as hi-z and does not have an external pull-down.
|
||||
* To ensure proper power sequencing for the FPMCU device, reset signal is driven low
|
||||
* early on in bootblock, followed by enabling of power. Reset signal is deasserted
|
||||
* later on in ramstage. Since reset signal is asserted in bootblock, it results in
|
||||
* FPMCU not working after a S3 resume. This is a known issue.
|
||||
*/
|
||||
PAD_CFG_GPO(GPP_D1, 0, DEEP),
|
||||
/* D2 : ISH_GP2 ==> EN_FP_PWR */
|
||||
PAD_CFG_GPO(GPP_D2, 1, DEEP),
|
||||
/* E15 : RSVD_TP ==> PCH_WP_OD */
|
||||
PAD_CFG_GPI_GPIO_DRIVER(GPP_E15, NONE, DEEP),
|
||||
/* H10 : UART0_RXD ==> UART_PCH_RX_DBG_TX */
|
||||
PAD_CFG_NF(GPP_H10, NONE, DEEP, NF2),
|
||||
/* H11 : UART0_TXD ==> UART_PCH_TX_DBG_RX */
|
||||
PAD_CFG_NF(GPP_H11, NONE, DEEP, NF2),
|
||||
/* H13 : I2C7_SCL ==> EN_PP3300_SD */
|
||||
PAD_CFG_GPO(GPP_H13, 1, DEEP),
|
||||
};
|
||||
|
||||
const struct pad_config *__weak variant_gpio_table(size_t *num)
|
||||
{
|
||||
*num = ARRAY_SIZE(gpio_table);
|
||||
return gpio_table;
|
||||
}
|
||||
|
||||
const struct pad_config *__weak variant_gpio_override_table(size_t *num)
|
||||
{
|
||||
*num = 0;
|
||||
return NULL;
|
||||
}
|
||||
|
||||
const struct pad_config *__weak variant_early_gpio_table(size_t *num)
|
||||
{
|
||||
*num = ARRAY_SIZE(early_gpio_table);
|
||||
return early_gpio_table;
|
||||
}
|
||||
|
||||
static const struct cros_gpio cros_gpios[] = {
|
||||
CROS_GPIO_REC_AL(CROS_GPIO_VIRTUAL, CROS_GPIO_DEVICE_NAME),
|
||||
CROS_GPIO_WP_AH(GPIO_PCH_WP, CROS_GPIO_DEVICE_NAME),
|
||||
};
|
||||
|
||||
const struct cros_gpio *__weak variant_cros_gpios(size_t *num)
|
||||
{
|
||||
*num = ARRAY_SIZE(cros_gpios);
|
||||
return cros_gpios;
|
||||
}
|
||||
|
|
@ -0,0 +1,43 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0-or-later */
|
||||
|
||||
#ifndef __BASEBOARD_EC_H__
|
||||
#define __BASEBOARD_EC_H__
|
||||
|
||||
#include <ec/ec.h>
|
||||
#include <ec/google/chromeec/ec_commands.h>
|
||||
#include <baseboard/gpio.h>
|
||||
|
||||
#define MAINBOARD_EC_SCI_EVENTS \
|
||||
(EC_HOST_EVENT_MASK(EC_HOST_EVENT_THERMAL_THRESHOLD) |\
|
||||
EC_HOST_EVENT_MASK(EC_HOST_EVENT_THROTTLE_START) |\
|
||||
EC_HOST_EVENT_MASK(EC_HOST_EVENT_THROTTLE_STOP) |\
|
||||
EC_HOST_EVENT_MASK(EC_HOST_EVENT_USB_CHARGER) |\
|
||||
EC_HOST_EVENT_MASK(EC_HOST_EVENT_MKBP) |\
|
||||
EC_HOST_EVENT_MASK(EC_HOST_EVENT_PD_MCU) |\
|
||||
EC_HOST_EVENT_MASK(EC_HOST_EVENT_MODE_CHANGE) |\
|
||||
EC_HOST_EVENT_MASK(EC_HOST_EVENT_USB_MUX))
|
||||
#define MAINBOARD_EC_SMI_EVENTS 0
|
||||
/* EC can wake from S5 with power button */
|
||||
#define MAINBOARD_EC_S5_WAKE_EVENTS \
|
||||
(EC_HOST_EVENT_MASK(EC_HOST_EVENT_POWER_BUTTON))
|
||||
/* EC can wake from S3 with power button */
|
||||
#define MAINBOARD_EC_S3_WAKE_EVENTS (MAINBOARD_EC_S5_WAKE_EVENTS)
|
||||
#define MAINBOARD_EC_S0IX_WAKE_EVENTS \
|
||||
(MAINBOARD_EC_S3_WAKE_EVENTS |\
|
||||
EC_HOST_EVENT_MASK(EC_HOST_EVENT_HANG_DETECT))
|
||||
/* Log EC wake events plus EC shutdown events */
|
||||
#define MAINBOARD_EC_LOG_EVENTS \
|
||||
(EC_HOST_EVENT_MASK(EC_HOST_EVENT_THERMAL_SHUTDOWN) |\
|
||||
EC_HOST_EVENT_MASK(EC_HOST_EVENT_PANIC))
|
||||
/*
|
||||
* ACPI related definitions for ASL code.
|
||||
*/
|
||||
#define EC_ENABLE_WAKE_PIN GPE_EC_WAKE
|
||||
/* Enable EC backed PD MCU device in ACPI */
|
||||
#define EC_ENABLE_PD_MCU_DEVICE
|
||||
#define SIO_EC_MEMMAP_ENABLE /* EC Memory Map Resources */
|
||||
#define SIO_EC_HOST_ENABLE /* EC Host Interface Resources */
|
||||
|
||||
#define EC_ENABLE_SYNC_IRQ /* Enable tight timestamp / wake support */
|
||||
|
||||
#endif /* __BASEBOARD_EC_H__ */
|
||||
|
|
@ -0,0 +1,22 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0-or-later */
|
||||
|
||||
#ifndef __BASEBOARD_GPIO_H__
|
||||
#define __BASEBOARD_GPIO_H__
|
||||
|
||||
#include <soc/gpe.h>
|
||||
#include <soc/gpio.h>
|
||||
|
||||
/* eSPI virtual wire reporting */
|
||||
#define EC_SCI_GPI GPE0_ESPI
|
||||
/* EC wake is EC_PCH_INT which is routed to GPP_F17 pin */
|
||||
#define GPE_EC_WAKE GPE0_DW2_17
|
||||
/* WP signal to PCH */
|
||||
#define GPIO_PCH_WP GPP_E15
|
||||
/* EC in RW or RO */
|
||||
#define GPIO_EC_IN_RW GPP_F18
|
||||
/* Used to gate SoC's SLP_S0# signal */
|
||||
#define GPIO_SLP_S0_GATE GPP_F9
|
||||
/* GPIO IRQ for tight timestamps / wake support */
|
||||
#define EC_SYNC_IRQ GPP_F17_IRQ
|
||||
|
||||
#endif /* __BASEBOARD_GPIO_H__ */
|
||||
|
|
@ -0,0 +1,8 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0-or-later */
|
||||
|
||||
#ifndef MAINBOARD_EC_H
|
||||
#define MAINBOARD_EC_H
|
||||
|
||||
#include <baseboard/ec.h>
|
||||
|
||||
#endif /* MAINBOARD_GPIO_H */
|
||||
|
|
@ -0,0 +1,8 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0-or-later */
|
||||
|
||||
#ifndef __MAINBOARD_GPIO_H__
|
||||
#define __MAINBOARD_GPIO_H__
|
||||
|
||||
#include <baseboard/gpio.h>
|
||||
|
||||
#endif /* __MAINBOARD_GPIO_H__ */
|
||||
|
|
@ -0,0 +1,6 @@
|
|||
chip soc/intel/alderlake
|
||||
|
||||
device domain 0 on
|
||||
end
|
||||
|
||||
end
|
||||
Loading…
Reference in New Issue