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mb/google/nyan/devicetree.cb: Correct some comments 

Use a consistent spelling for SoC (System-on-a-Chip), and fix a few
minor typos.

Change-Id: I29eacc9e93b2eb686ce945de0173844ef5eae1b9
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38063
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
This commit is contained in:
Angel Pons 2020-01-01 18:54:31 +01:00 committed by Nico Huber
parent b6df6b065c
commit c045a02174
3 changed files with 15 additions and 15 deletions
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10
src/mainboard/google/nyan/devicetree.cb
View File

@ -15,12 +15,12 @@
chip soc/nvidia/tegra124
device cpu_cluster 0 on end
# N.B. We ae not using the device tree in an effective way.
# We need to change this in future such that the on-soc
# N.B. We are not using the device tree in an effective way.
# We need to change this in future such that the on-SoC
# devices are 'chips', which will allow us to go at them
# in parallel. This is even easier on the ARM SOCs since there
# in parallel. This is even easier on the ARM SoCs since there
# are no single-access resources such as the infamous
# cf8/cfc registers found on PCs.
# 0xcf8/0xcfc registers found on PCs.
register "display_controller" = "TEGRA_ARM_DISPLAYA"
register "xres" = "1366"
register "yres" = "768"
@ -39,7 +39,7 @@ chip soc/nvidia/tegra124
register "panel_vdd_gpio" = "0"
register "pwm" = "1"
# various panel delay time
# Various panel delay times
register "vdd_delay_ms" = "200"
register "pwm_to_bl_delay_ms" = "10"
register "vdd_to_hpd_delay_ms" = "200"

10
src/mainboard/google/nyan_big/devicetree.cb
View File

@ -15,12 +15,12 @@
chip soc/nvidia/tegra124
device cpu_cluster 0 on end
# N.B. We ae not using the device tree in an effective way.
# We need to change this in future such that the on-soc
# N.B. We are not using the device tree in an effective way.
# We need to change this in future such that the on-SoC
# devices are 'chips', which will allow us to go at them
# in parallel. This is even easier on the ARM SOCs since there
# in parallel. This is even easier on the ARM SoCs since there
# are no single-access resources such as the infamous
# cf8/cfc registers found on PCs.
# 0xcf8/0xcfc registers found on PCs.
register "display_controller" = "TEGRA_ARM_DISPLAYA"
register "xres" = "1366"
register "yres" = "768"
@ -39,7 +39,7 @@ chip soc/nvidia/tegra124
register "panel_vdd_gpio" = "0"
register "pwm" = "1"
# various panel delay time
# Various panel delay times
register "vdd_delay_ms" = "200"
register "pwm_to_bl_delay_ms" = "10"
register "vdd_to_hpd_delay_ms" = "200"

10
src/mainboard/google/nyan_blaze/devicetree.cb
View File

@ -15,12 +15,12 @@
chip soc/nvidia/tegra124
device cpu_cluster 0 on end
# N.B. We ae not using the device tree in an effective way.
# We need to change this in future such that the on-soc
# N.B. We are not using the device tree in an effective way.
# We need to change this in future such that the on-SoC
# devices are 'chips', which will allow us to go at them
# in parallel. This is even easier on the ARM SOCs since there
# in parallel. This is even easier on the ARM SoCs since there
# are no single-access resources such as the infamous
# cf8/cfc registers found on PCs.
# 0xcf8/0xcfc registers found on PCs.
register "display_controller" = "TEGRA_ARM_DISPLAYA"
register "xres" = "1366"
register "yres" = "768"
@ -39,7 +39,7 @@ chip soc/nvidia/tegra124
register "panel_vdd_gpio" = "0"
register "pwm" = "1"
# various panel delay time
# Various panel delay times
register "vdd_delay_ms" = "200"
register "pwm_to_bl_delay_ms" = "10"
register "vdd_to_hpd_delay_ms" = "200"