armv7/exynos: Fix and remove memory reset workarounds
The memory corruption problem in Exynos suspend/resume process is caused by two things together: PHY_RESET and MRS command. After stop sending MRS on resume, we can now remove the workaround of skipping PHY_RESET. Change-Id: I64acc27c1d2bb549ae6ad7d32ecda94b0355972c Reviewed-on: https://gerrit.chromium.org/gerrit/64736 Tested-by: Hung-Te Lin <hungte@chromium.org> Reviewed-by: David Hendricks <dhendrix@chromium.org> Commit-Queue: Hung-Te Lin <hungte@chromium.org> Reviewed-on: http://review.coreboot.org/4433 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
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@ -158,8 +158,14 @@ int ddr3_mem_ctrl_init(struct mem_timings *mem, unsigned long mem_iv_size,
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/* Send PALL command */
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/* Send PALL command */
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dmc_config_prech(mem, dmc);
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dmc_config_prech(mem, dmc);
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/* Send NOP, MRS and ZQINIT commands */
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if (mem_reset) {
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/* Send NOP, MRS and ZQINIT commands.
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* Sending MRS command will reset the DRAM. We should not be
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* reseting the DRAM after resume, this will lead to memory
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* corruption as DRAM content is lost after DRAM reset
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*/
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dmc_config_mrs(mem, dmc);
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dmc_config_mrs(mem, dmc);
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}
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if (mem->gate_leveling_enable) {
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if (mem->gate_leveling_enable) {
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val = PHY_CON0_RESET_VAL;
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val = PHY_CON0_RESET_VAL;
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@ -184,9 +184,15 @@ int ddr3_mem_ctrl_init(struct mem_timings *mem, int interleave_size, int reset)
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writel(mem->timing_power, &drex0->timingpower);
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writel(mem->timing_power, &drex0->timingpower);
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writel(mem->timing_power, &drex1->timingpower);
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writel(mem->timing_power, &drex1->timingpower);
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/* Send NOP, MRS and ZQINIT commands */
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/* Send NOP, MRS and ZQINIT commands.
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* Sending MRS command will reset the DRAM. We should not be
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* reseting the DRAM after resume, this will lead to memory
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* corruption as DRAM content is lost after DRAM reset.
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*/
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if (reset) {
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dmc_config_mrs(mem, drex0);
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dmc_config_mrs(mem, drex0);
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dmc_config_mrs(mem, drex1);
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dmc_config_mrs(mem, drex1);
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}
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if (mem->gate_leveling_enable) {
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if (mem->gate_leveling_enable) {
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@ -141,13 +141,6 @@ static void setup_memory(struct mem_timings *mem, int is_resume)
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mem->mpll_mdiv,
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mem->mpll_mdiv,
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mem->frequency_mhz);
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mem->frequency_mhz);
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/* FIXME Currently memory initialization with mem_reset on normal boot
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* will cause resume to fail (even if we don't do mem_reset on resume),
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* and the workaround is to temporarily always enable "is_resume".
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* This should be removed when the root cause of resume issue is found.
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*/
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is_resume = 1;
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if (ddr3_mem_ctrl_init(mem, DMC_INTERLEAVE_SIZE, !is_resume)) {
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if (ddr3_mem_ctrl_init(mem, DMC_INTERLEAVE_SIZE, !is_resume)) {
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die("Failed to initialize memory controller.\n");
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die("Failed to initialize memory controller.\n");
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}
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}
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