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armv7/exynos: Fix and remove memory reset workarounds 

The memory corruption problem in Exynos suspend/resume process is caused by two
things together: PHY_RESET and MRS command.

After stop sending MRS on resume, we can now remove the workaround of skipping
PHY_RESET.

Change-Id: I64acc27c1d2bb549ae6ad7d32ecda94b0355972c
Reviewed-on: https://gerrit.chromium.org/gerrit/64736
Tested-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-by: David Hendricks <dhendrix@chromium.org>
Commit-Queue: Hung-Te Lin <hungte@chromium.org>
Reviewed-on: http://review.coreboot.org/4433
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
This commit is contained in:
Hung-Te Lin 2013-08-06 10:48:48 +08:00 committed by Patrick Georgi
parent c0d5eb2a33
commit c0491d4fb5
3 changed files with 17 additions and 12 deletions
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10
src/cpu/samsung/exynos5250/dmc_init_ddr3.c
View File

@ -158,8 +158,14 @@ int ddr3_mem_ctrl_init(struct mem_timings *mem, unsigned long mem_iv_size,
/* Send PALL command */
dmc_config_prech(mem, dmc);
/* Send NOP, MRS and ZQINIT commands */
dmc_config_mrs(mem, dmc);
if (mem_reset) {
/* Send NOP, MRS and ZQINIT commands.
* Sending MRS command will reset the DRAM. We should not be
* reseting the DRAM after resume, this will lead to memory
* corruption as DRAM content is lost after DRAM reset
*/
dmc_config_mrs(mem, dmc);
}
if (mem->gate_leveling_enable) {
val = PHY_CON0_RESET_VAL;

12
src/cpu/samsung/exynos5420/dmc_init_ddr3.c
View File

@ -184,9 +184,15 @@ int ddr3_mem_ctrl_init(struct mem_timings *mem, int interleave_size, int reset)
writel(mem->timing_power, &drex0->timingpower);
writel(mem->timing_power, &drex1->timingpower);
/* Send NOP, MRS and ZQINIT commands */
dmc_config_mrs(mem, drex0);
dmc_config_mrs(mem, drex1);
/* Send NOP, MRS and ZQINIT commands.
* Sending MRS command will reset the DRAM. We should not be
* reseting the DRAM after resume, this will lead to memory
* corruption as DRAM content is lost after DRAM reset.
*/
if (reset) {
dmc_config_mrs(mem, drex0);
dmc_config_mrs(mem, drex1);
}
if (mem->gate_leveling_enable) {

7
src/mainboard/google/snow/romstage.c
View File

@ -141,13 +141,6 @@ static void setup_memory(struct mem_timings *mem, int is_resume)
mem->mpll_mdiv,
mem->frequency_mhz);
/* FIXME Currently memory initialization with mem_reset on normal boot
* will cause resume to fail (even if we don't do mem_reset on resume),
* and the workaround is to temporarily always enable "is_resume".
* This should be removed when the root cause of resume issue is found.
*/
is_resume = 1;
if (ddr3_mem_ctrl_init(mem, DMC_INTERLEAVE_SIZE, !is_resume)) {
die("Failed to initialize memory controller.\n");
}