mb/google/brya/variants/redrix: Configure GPIOs according to schematics
Update initial gpio configuration for redrix BUG=b:192052098 TEST=FW_NAME=redrix emerge-brya coreboot Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com> Change-Id: I2294fb3bdba832677038cfe24b5014014c7f03e9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56428 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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# SPDX-License-Identifier: GPL-2.0-only
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bootblock-y += gpio.c
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ramstage-y += gpio.c
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/* SPDX-License-Identifier: GPL-2.0-or-later */
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#include <baseboard/gpio.h>
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#include <baseboard/variants.h>
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#include <commonlib/helpers.h>
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#include <soc/gpio.h>
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#include <vendorcode/google/chromeos/chromeos.h>
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/* Pad configuration in ramstage */
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static const struct pad_config override_gpio_table[] = {
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/* A17 : DISP_MISCC ==> NC */
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PAD_NC(GPP_A17, NONE),
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/* A19 : DDSP_HPD1 ==> NC */
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PAD_NC(GPP_A19, NONE),
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/* A20 : DDSP_HPD2 ==> NC */
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PAD_NC(GPP_A20, NONE),
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/* A21 : DDPC_CTRCLK ==> NC */
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PAD_NC(GPP_A21, NONE),
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/* A22 : DDPC_CTRLDATA ==> NC */
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PAD_NC(GPP_A22, NONE),
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/* B3 : PROC_GP2 ==> NC */
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PAD_NC(GPP_B3, NONE),
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/* B15 : TIME_SYNC0 ==> NC */
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PAD_NC(GPP_B15, NONE),
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/* C3 : SML0CLK ==> NC */
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PAD_NC(GPP_C3, NONE),
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/* C4 : SML0DATA ==> NC */
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PAD_NC(GPP_C4, NONE),
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/* D7 : SRCCLKREQ2# ==> NC */
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PAD_NC(GPP_D7, NONE),
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/* D13 : ISH_UART0_RXD ==> NC */
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PAD_NC(GPP_D13, NONE),
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/* E0 : SATAXPCIE0 ==> NC */
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PAD_NC(GPP_E0, NONE),
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/* E3 : PROC_GP0 ==> NC */
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PAD_NC(GPP_E3, NONE),
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/* E7 : PROC_GP1 ==> NC */
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PAD_NC(GPP_E7, NONE),
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/* E20 : DDP2_CTRLCLK ==> NC */
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PAD_NC(GPP_E20, NONE),
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/* E22 : DDPA_CTRLCLK ==> NC */
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PAD_NC(GPP_E22, NONE),
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/* E23 : DDPA_CTRLDATA ==> NC */
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PAD_NC(GPP_E23, NONE),
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/* F20 : EXT_PWR_GATE# ==> NC */
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PAD_NC(GPP_F20, NONE),
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/* H3 : SX_EXIT_HOLDOFF# ==> NC */
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PAD_NC(GPP_H3, NONE),
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/* H20 : IMGCLKOUT1 ==> NC */
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PAD_NC(GPP_H20, NONE),
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/* H21 : IMGCLKOUT2 ==> Privacy screen */
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PAD_CFG_GPO(GPP_H21, 0, DEEP),
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/* R6 : I2S_PCH_TX_SPKR_RX ==> NC */
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PAD_NC(GPP_R6, NONE),
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/* R7 : I2S_PCH_RX_SPKR_TX ==> NC */
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PAD_NC(GPP_R7, NONE),
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/* S4 : SNDW2_CLK ==> NC */
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PAD_NC(GPP_S4, NONE),
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/* S5 : SNDW2_DATA ==> NC */
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PAD_NC(GPP_S5, NONE),
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/* S6 : SNDW3_CLK ==> NC */
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PAD_NC(GPP_S6, NONE),
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/* S7 : SNDW3_DATA ==> NC */
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PAD_NC(GPP_S7, NONE),
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};
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/* Early pad configuration in bootblock */
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static const struct pad_config early_gpio_table[] = {
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/* A13 : PMC_I2C_SCL ==> GSC_PCH_INT_ODL */
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PAD_CFG_GPI_APIC(GPP_A13, NONE, PLTRST, LEVEL, INVERT),
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/* B7 : ISH_12C1_SDA ==> PCH_I2C_TPM_SDA */
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PAD_CFG_NF(GPP_B7, NONE, DEEP, NF2),
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/* B8 : ISH_12C1_SCL ==> PCH_I2C_TPM_SCL */
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PAD_CFG_NF(GPP_B8, NONE, DEEP, NF2),
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/*
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* D1 : ISH_GP1 ==> FP_RST_ODL
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* FP_RST_ODL comes out of reset as hi-z and does not have an external pull-down.
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* To ensure proper power sequencing for the FPMCU device, reset signal is driven low
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* early on in bootblock, followed by enabling of power. Reset signal is deasserted
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* later on in ramstage. Since reset signal is asserted in bootblock, it results in
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* FPMCU not working after a S3 resume. This is a known issue.
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*/
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PAD_CFG_GPO(GPP_D1, 0, DEEP),
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/* D2 : ISH_GP2 ==> EN_FP_PWR */
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PAD_CFG_GPO(GPP_D2, 1, DEEP),
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/* E0 : SATAXPCIE0 ==> NC */
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PAD_NC(GPP_E0, NONE),
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/* E13 : THC0_SPI1_IO2 ==> MEM_CH_SEL */
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PAD_CFG_GPI(GPP_E13, NONE, DEEP),
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/* E15 : RSVD_TP ==> PCH_WP_OD */
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PAD_CFG_GPI_GPIO_DRIVER(GPP_E15, NONE, DEEP),
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/* E16 : RSVD_TP ==> WWAN_RST_L */
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PAD_CFG_GPO(GPP_E16, 0, DEEP),
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/* H10 : UART0_RXD ==> UART_PCH_RX_DBG_TX */
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PAD_CFG_NF(GPP_H10, NONE, DEEP, NF2),
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/* H11 : UART0_TXD ==> UART_PCH_TX_DBG_RX */
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PAD_CFG_NF(GPP_H11, NONE, DEEP, NF2),
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/* H13 : I2C7_SCL ==> EN_PP3300_SD */
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PAD_CFG_GPO(GPP_H13, 1, DEEP),
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};
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const struct pad_config *variant_gpio_override_table(size_t *num)
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{
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*num = ARRAY_SIZE(override_gpio_table);
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return override_gpio_table;
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}
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const struct pad_config *variant_early_gpio_table(size_t *num)
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{
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*num = ARRAY_SIZE(early_gpio_table);
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return early_gpio_table;
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}
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