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nyan*: pinmux: fix PWM1/2 conflicts 

GPIO_PU4/PH1 and _PU5/PH2 were set to use the same PWM1/2 SFIO.
Even though no problems were caused by this, correct it here
so we get a conflict-free pinmux map.

BUG=chrome-os-partner:27091
BRANCH=none
TEST=Built and booted on Nyan, ran TegraShell "pinmux check"
and saw no conflicts.

Original-Change-Id: Ib16341aa0c92b9a078d7f3254d4151e9592f40b0
Original-Signed-off-by: Tom Warren <twarren@nvidia.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/194582
Original-Reviewed-by: David Hendricks <dhendrix@chromium.org>
(cherry picked from commit e06a5a62d381f803dd6574787795a51ce1f1fe74)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>

Change-Id: I055359dc80c0c878ba5f5faac17884a5506a826c
Reviewed-on: http://review.coreboot.org/7759
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
This commit is contained in:
Tom Warren 2014-04-14 10:01:21 -07:00 committed by Marc Jones
parent 846f344226
commit c05a90595d
3 changed files with 13 additions and 1 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

6
src/mainboard/google/nyan/romstage.c
View File

@ -1,7 +1,7 @@
/* /*
* This file is part of the coreboot project. * This file is part of the coreboot project.
* *
* Copyright 2013 Google Inc. * Copyright 2014 Google Inc.
* *
* This program is free software; you can redistribute it and/or modify * This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by * it under the terms of the GNU General Public License as published by
@ -94,6 +94,10 @@ static void setup_pinmux(void)
// EC in RW. // EC in RW.
gpio_input_pullup(GPIO(U4)); gpio_input_pullup(GPIO(U4));
// route PU4/5 to GMI to remove conflict w/PWM1/2.
pinmux_set_config(PINMUX_GPIO_PU4_INDEX, PINMUX_GPIO_PU4_FUNC_NOR); //s/b GMI
pinmux_set_config(PINMUX_GPIO_PU5_INDEX, PINMUX_GPIO_PU5_FUNC_NOR); //s/b GMI
// SOC and TPM reset GPIO, active low. // SOC and TPM reset GPIO, active low.
gpio_output(GPIO(I5), 1); gpio_output(GPIO(I5), 1);

4
src/mainboard/google/nyan_big/romstage.c
View File

@ -94,6 +94,10 @@ static void setup_pinmux(void)
// EC in RW. // EC in RW.
gpio_input_pullup(GPIO(U4)); gpio_input_pullup(GPIO(U4));
// route PU4/5 to GMI to remove conflict w/PWM1/2.
pinmux_set_config(PINMUX_GPIO_PU4_INDEX, PINMUX_GPIO_PU4_FUNC_NOR); //s/b GMI
pinmux_set_config(PINMUX_GPIO_PU5_INDEX, PINMUX_GPIO_PU5_FUNC_NOR); //s/b GMI
// SOC and TPM reset GPIO, active low. // SOC and TPM reset GPIO, active low.
gpio_output(GPIO(I5), 1); gpio_output(GPIO(I5), 1);

4
src/mainboard/google/nyan_blaze/romstage.c
View File

@ -94,6 +94,10 @@ static void setup_pinmux(void)
// EC in RW. // EC in RW.
gpio_input_pullup(GPIO(U4)); gpio_input_pullup(GPIO(U4));
// route PU4/5 to GMI to remove conflict w/PWM1/2.
pinmux_set_config(PINMUX_GPIO_PU4_INDEX, PINMUX_GPIO_PU4_FUNC_NOR); //s/b GMI
pinmux_set_config(PINMUX_GPIO_PU5_INDEX, PINMUX_GPIO_PU5_FUNC_NOR); //s/b GMI
// SOC and TPM reset GPIO, active low. // SOC and TPM reset GPIO, active low.
gpio_output(GPIO(I5), 1); gpio_output(GPIO(I5), 1);