soc/intel/braswell/acpi: Clean OpRegion up
Reorder code and put platform specific bits into update_igd_opregion. Get rid of get_fsp_vbt and init_igd_opregion. Write GMA opregion in case a VBT was provided, even when no FSP_GOP is to be run. Use SOC_INTEL_COMMON_GFX_OPREGION to reduce code duplication. Change-Id: Ibabeb05a9d3d776b73f6885dcca846d5001116e7 Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://review.coreboot.org/20221 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
This commit is contained in:
Patrick Rudolph
Matt DeVillier
parent
7c60498de7
commit
c060fb5aac
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@ -48,6 +48,7 @@ config CPU_SPECIFIC_OPTIONS
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select HAVE_SPI_CONSOLE_SUPPORT
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select HAVE_FSP_GOP
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select GENERIC_GPIO_LIB
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select SOC_INTEL_COMMON_GFX_OPREGION
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config VBOOT
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select VBOOT_STARTS_IN_ROMSTAGE
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@ -31,7 +31,7 @@
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#include <device/pci.h>
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#include <device/pci_ids.h>
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#include <ec/google/chromeec/ec.h>
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#include <fsp/gop.h>
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#include <soc/intel/common/opregion.h>
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#include <rules.h>
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#include <soc/acpi.h>
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#include <soc/gfx.h>
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@ -473,6 +473,46 @@ unsigned long acpi_madt_irq_overrides(unsigned long current)
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return current;
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}
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/* Initialize IGD OpRegion, called from ACPI code */
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static int update_igd_opregion(igd_opregion_t *opregion)
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{
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u16 reg16;
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struct device *igd;
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/* TODO Initialize Mailbox 1 */
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/* TODO Initialize Mailbox 3 */
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opregion->mailbox3.bclp = IGD_BACKLIGHT_BRIGHTNESS;
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opregion->mailbox3.pfit = IGD_FIELD_VALID | IGD_PFIT_STRETCH;
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opregion->mailbox3.pcft = 0; /* should be (IMON << 1) & 0x3e */
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opregion->mailbox3.cblv = IGD_FIELD_VALID | IGD_INITIAL_BRIGHTNESS;
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opregion->mailbox3.bclm[0] = IGD_WORD_FIELD_VALID + 0x0000;
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opregion->mailbox3.bclm[1] = IGD_WORD_FIELD_VALID + 0x0a19;
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opregion->mailbox3.bclm[2] = IGD_WORD_FIELD_VALID + 0x1433;
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opregion->mailbox3.bclm[3] = IGD_WORD_FIELD_VALID + 0x1e4c;
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opregion->mailbox3.bclm[4] = IGD_WORD_FIELD_VALID + 0x2866;
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opregion->mailbox3.bclm[5] = IGD_WORD_FIELD_VALID + 0x327f;
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opregion->mailbox3.bclm[6] = IGD_WORD_FIELD_VALID + 0x3c99;
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opregion->mailbox3.bclm[7] = IGD_WORD_FIELD_VALID + 0x46b2;
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opregion->mailbox3.bclm[8] = IGD_WORD_FIELD_VALID + 0x50cc;
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opregion->mailbox3.bclm[9] = IGD_WORD_FIELD_VALID + 0x5ae5;
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opregion->mailbox3.bclm[10] = IGD_WORD_FIELD_VALID + 0x64ff;
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/*
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* TODO This needs to happen in S3 resume, too.
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* Maybe it should move to the finalize handler
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*/
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igd = dev_find_slot(0, PCI_DEVFN(GFX_DEV, GFX_FUNC));
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pci_write_config32(igd, ASLS, (u32)opregion);
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reg16 = pci_read_config16(igd, SWSCI);
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reg16 &= ~(1 << 0);
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reg16 |= (1 << 15);
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pci_write_config16(igd, SWSCI, reg16);
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return 0;
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}
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unsigned long southcluster_write_acpi_tables(device_t device,
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unsigned long current,
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struct acpi_rsdp *rsdp)
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@ -482,12 +522,13 @@ unsigned long southcluster_write_acpi_tables(device_t device,
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current = acpi_write_hpet(device, current, rsdp);
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current = acpi_align_current(current);
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if (IS_ENABLED(CONFIG_RUN_FSP_GOP)) {
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if (IS_ENABLED(CONFIG_INTEL_GMA_ADD_VBT_DATA_FILE)) {
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igd_opregion_t *opregion;
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printk(BIOS_DEBUG, "ACPI: * IGD OpRegion\n");
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opregion = (igd_opregion_t *)current;
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init_igd_opregion(opregion);
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update_igd_opregion(opregion);
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current += sizeof(igd_opregion_t);
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current = acpi_align_current(current);
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}
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@ -543,74 +584,3 @@ void southcluster_inject_dsdt(device_t device)
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__attribute__((weak)) void acpi_create_serialio_ssdt(acpi_header_t *ssdt)
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{
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}
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/* Reading VBT table from flash */
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static void get_fsp_vbt(igd_opregion_t *opregion)
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{
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const optionrom_vbt_t *vbt;
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uint32_t vbt_len;
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vbt = fsp_get_vbt(&vbt_len);
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if (!vbt)
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die("vbt data not found");
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memcpy(opregion->header.vbios_version, vbt->coreblock_biosbuild, 4);
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memcpy(opregion->vbt.gvd1, vbt, vbt->hdr_vbt_size <
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sizeof(opregion->vbt.gvd1) ? vbt->hdr_vbt_size :
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sizeof(opregion->vbt.gvd1));
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}
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/* Initialize IGD OpRegion, called from ACPI code */
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int init_igd_opregion(igd_opregion_t *opregion)
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{
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device_t igd;
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u16 reg16;
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memset(opregion, 0, sizeof(igd_opregion_t));
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/* FIXME if IGD is disabled, we should exit here. */
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memcpy(&opregion->header.signature, IGD_OPREGION_SIGNATURE,
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sizeof(IGD_OPREGION_SIGNATURE));
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/* 8kb */
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opregion->header.size = sizeof(igd_opregion_t) / 1024;
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opregion->header.version = IGD_OPREGION_VERSION;
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/* FIXME We just assume we're mobile for now */
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opregion->header.mailboxes = MAILBOXES_MOBILE;
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/* TODO Initialize Mailbox 1 */
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/* TODO Initialize Mailbox 3 */
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opregion->mailbox3.bclp = IGD_BACKLIGHT_BRIGHTNESS;
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opregion->mailbox3.pfit = IGD_FIELD_VALID | IGD_PFIT_STRETCH;
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opregion->mailbox3.pcft = 0; /* should be (IMON << 1) & 0x3e */
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opregion->mailbox3.cblv = IGD_FIELD_VALID | IGD_INITIAL_BRIGHTNESS;
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opregion->mailbox3.bclm[0] = IGD_WORD_FIELD_VALID + 0x0000;
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opregion->mailbox3.bclm[1] = IGD_WORD_FIELD_VALID + 0x0a19;
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opregion->mailbox3.bclm[2] = IGD_WORD_FIELD_VALID + 0x1433;
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opregion->mailbox3.bclm[3] = IGD_WORD_FIELD_VALID + 0x1e4c;
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opregion->mailbox3.bclm[4] = IGD_WORD_FIELD_VALID + 0x2866;
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opregion->mailbox3.bclm[5] = IGD_WORD_FIELD_VALID + 0x327f;
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opregion->mailbox3.bclm[6] = IGD_WORD_FIELD_VALID + 0x3c99;
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opregion->mailbox3.bclm[7] = IGD_WORD_FIELD_VALID + 0x46b2;
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opregion->mailbox3.bclm[8] = IGD_WORD_FIELD_VALID + 0x50cc;
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opregion->mailbox3.bclm[9] = IGD_WORD_FIELD_VALID + 0x5ae5;
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opregion->mailbox3.bclm[10] = IGD_WORD_FIELD_VALID + 0x64ff;
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get_fsp_vbt(opregion);
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/*
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* TODO This needs to happen in S3 resume, too.
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* Maybe it should move to the finalize handler
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*/
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igd = dev_find_slot(0, PCI_DEVFN(GFX_DEV, GFX_FUNC));
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pci_write_config32(igd, ASLS, (u32)opregion);
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reg16 = pci_read_config16(igd, SWSCI);
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reg16 &= ~(1 << 0);
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reg16 |= (1 << 15);
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pci_write_config16(igd, SWSCI, reg16);
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return 0;
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}
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@ -20,9 +20,6 @@
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#include <arch/acpi.h>
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#include <soc/nvs.h>
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#include <fsp/gma.h>
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int init_igd_opregion(igd_opregion_t *igd_opregion);
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void acpi_create_serialio_ssdt(acpi_header_t *ssdt);
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void acpi_fill_in_fadt(acpi_fadt_t *fadt);
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unsigned long acpi_madt_irq_overrides(unsigned long current);
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