soc/mediatek: Include sdram_info in ddr_base_info
Sync dramc_param.h with private repo mtk-dramk (CL:*3751861). BUG=none TEST=emerge-asurada coreboot TEST=Hayato boots with fast calibration BRANCH=asurada Change-Id: I79541f66ce68a75147c22b83a456e6268ca1485e Signed-off-by: Yu-Ping Wu <yupingso@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52257 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Hung-Te Lin <hungte@chromium.org>
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@ -19,15 +19,15 @@ bool is_dvfs_enabled(void)
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u32 get_ddr_geometry(void)
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{
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dramc_info("dram_init: ddr_geometry: %d\n",
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dramc_params->dramc_datas.ddr_info.ddr_geometry);
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return dramc_params->dramc_datas.ddr_info.ddr_geometry;
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dramc_params->dramc_datas.ddr_info.sdram.ddr_geometry);
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return dramc_params->dramc_datas.ddr_info.sdram.ddr_geometry;
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}
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u32 get_ddr_type(void)
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{
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dramc_info("dram_init: ddr_type: %d\n",
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dramc_params->dramc_datas.ddr_info.ddr_type);
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return dramc_params->dramc_datas.ddr_info.ddr_type;
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dramc_params->dramc_datas.ddr_info.sdram.ddr_type);
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return dramc_params->dramc_datas.ddr_info.sdram.ddr_type;
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}
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void init_dram_by_params(struct dramc_param *dparam)
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@ -4,8 +4,8 @@
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#define __SOC_MEDIATEK_DRAMC_PARAM_H__
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/*
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* This file is shared between coreboot and dram blob. Any change in this file
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* should be synced to the other repository.
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* NOTE: This file is shared between coreboot and dram blob. Any change in this
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* file should be synced to the other repository.
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*/
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#include <stdint.h>
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@ -27,21 +27,21 @@ enum DRAMC_PARAM_STATUS_CODES {
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DRAMC_ERR_FAST_CALIBRATION,
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};
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enum DRAMC_PARAM_DVFS_FLAG {
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DRAMC_DISABLE_DVFS,
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DRAMC_ENABLE_DVFS,
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};
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enum DRAMC_PARAM_FLAGS {
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DRAMC_FLAG_HAS_SAVED_DATA = 0x0001,
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};
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enum DRAMC_PARAM_DDR_TYPE {
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enum SDRAM_DVFS_FLAG {
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DRAMC_DISABLE_DVFS,
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DRAMC_ENABLE_DVFS,
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};
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enum SDRAM_DDR_TYPE {
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DDR_TYPE_DISCRETE,
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DDR_TYPE_EMCP,
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};
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enum DRAMC_PARAM_GEOMETRY_TYPE {
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enum SDRAM_DDR_GEOMETRY_TYPE {
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DDR_TYPE_2CH_2RK_4GB_2_2,
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DDR_TYPE_2CH_2RK_6GB_3_3,
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DDR_TYPE_2CH_2RK_8GB_4_4_BYTE,
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@ -50,10 +50,10 @@ enum DRAMC_PARAM_GEOMETRY_TYPE {
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DDR_TYPE_2CH_2RK_8GB_4_4,
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};
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enum DRAM_PARAM_VOLTAGE_TYPE {
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DRAM_VOLTAGE_NVCORE_NVDRAM,
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DRAM_VOLTAGE_HVCORE_HVDRAM,
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DRAM_VOLTAGE_LVCORE_LVDRAM,
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enum SDRAM_VOLTAGE_TYPE {
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SDRAM_VOLTAGE_NVCORE_NVDRAM,
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SDRAM_VOLTAGE_HVCORE_HVDRAM,
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SDRAM_VOLTAGE_LVCORE_LVDRAM,
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};
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struct dramc_param_header {
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@ -63,6 +63,11 @@ struct dramc_param_header {
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u16 flags; /* DRAMC_PARAM_FLAGS, update in the dram blob */
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};
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struct sdram_info {
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u32 ddr_type; /* SDRAM_DDR_TYPE */
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u32 ddr_geometry; /* SDRAM_DDR_GEOMETRY_TYPE */
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};
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struct sdram_params {
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u32 rank_num;
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u16 num_dlycell_perT;
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@ -118,10 +123,9 @@ struct emi_mdl {
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};
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struct ddr_base_info {
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u32 config_dvfs; /* DRAMC_PARAM_DVFS_FLAG */
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u32 ddr_type; /* DRAMC_PARAM_DDR_TYPE */
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u32 ddr_geometry; /* DRAMC_PARAM_GEOMETRY_TYPE */
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u32 voltage_type; /* DRAM_PARAM_VOLTAGE_TYPE */
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u32 config_dvfs; /* SDRAM_DVFS_FLAG */
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struct sdram_info sdram;
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u32 voltage_type; /* SDRAM_VOLTAGE_TYPE */
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u32 support_ranks;
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u64 rank_size[RANK_MAX];
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struct emi_mdl emi_config;
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@ -139,11 +143,6 @@ struct dramc_param {
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struct dramc_data dramc_datas;
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};
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struct sdram_info {
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u32 ddr_geometry; /* DRAMC_PARAM_GEOMETRY_TYPE */
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u32 ddr_type; /* DRAMC_PARAM_DDR_TYPE */
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};
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const struct sdram_info *get_sdram_config(void);
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struct dramc_param *get_dramc_param_from_blob(void *blob);
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void dump_param_header(const void *blob);
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@ -156,12 +156,12 @@ static void mem_init_set_default_config(struct dramc_param *dparam,
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type = dram_info->ddr_type;
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geometry = dram_info->ddr_geometry;
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dparam->dramc_datas.ddr_info.ddr_type = type;
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dparam->dramc_datas.ddr_info.sdram.ddr_type = type;
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if (CONFIG(MEDIATEK_DRAM_DVFS))
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dparam->dramc_datas.ddr_info.config_dvfs = DRAMC_ENABLE_DVFS;
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dparam->dramc_datas.ddr_info.ddr_geometry = geometry;
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dparam->dramc_datas.ddr_info.sdram.ddr_geometry = geometry;
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printk(BIOS_INFO, "DRAM-K: ddr_type: %s, config_dvfs: %d, ddr_geometry: %s\n",
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get_dram_type_str(type),
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