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soc/intel/skylake: Make use of common thermal code for SKL 

This patch ensures skylake soc is using common thermal code
from intel common block.

TEST=Build and boot soraka

Change-Id: I0812daa3536051918ccac973fde8d7f4f949609d
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34648
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Aamir Bohra <aamir.bohra@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Subrata Banik 2019-08-01 10:50:35 +05:30
parent 92dc391291
commit c077b2274b
13 changed files with 16 additions and 152 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

3
src/mainboard/google/poppy/variants/atlas/devicetree.cb
View File

@ -64,7 +64,6 @@ chip soc/intel/skylake
register "tdp_pl2_override" = "15"
register "psys_pmax" = "45"
register "tcc_offset" = "10"
register "pch_trip_temp" = "75"
register "pirqa_routing" = "PCH_IRQ11"
register "pirqb_routing" = "PCH_IRQ10"
@ -182,6 +181,7 @@ chip soc/intel/skylake
#| I2C2 | Trackpad |
#| I2C3 | Camera |
#| I2C4 | Audio |
#| pch_thermal_trip | PCH Trip Temperature |
#+-------------------+---------------------------+
register "common_soc_config" = "{
.chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT,
@ -217,6 +217,7 @@ chip soc/intel/skylake
.speed_mhz = 1,
.early_init = 1,
},
.pch_thermal_trip = 75,
}"
# Touchscreen
register "i2c_voltage[0]" = "I2C_VOLTAGE_3V3"

5
src/mainboard/google/poppy/variants/baseboard/devicetree.cb
View File

@ -177,6 +177,7 @@ chip soc/intel/skylake
#| I2C3 | Pen |
#| I2C4 | Camera |
#| I2C5 | Audio |
#| pch_thermal_trip | PCH Trip Temperature |
#+-------------------+---------------------------+
register "common_soc_config" = "{
.chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT,
@ -226,6 +227,7 @@ chip soc/intel/skylake
.sda_hold = 36,
},
},
.pch_thermal_trip = 75,
}"
# Touchscreen
@ -270,9 +272,6 @@ chip soc/intel/skylake
# Use default SD card detect GPIO configuration
register "sdcard_cd_gpio_default" = "GPP_E15"
# PCH Trip Temperature in degree C
register "pch_trip_temp" = "75"
device cpu_cluster 0 on
device lapic 0 on end
end

5
src/mainboard/google/poppy/variants/nami/devicetree.cb
View File

@ -219,6 +219,7 @@ chip soc/intel/skylake
#| I2C1 | Trackpad |
#| I2C2 | Pen |
#| I2C3 | Audio |
#| pch_thermal_trip | PCH Trip Temperature |
#+-------------------+---------------------------+
register "common_soc_config" = "{
.chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT,
@ -263,6 +264,7 @@ chip soc/intel/skylake
.sda_hold = 36,
},
},
.pch_thermal_trip = 75,
}"
# Must leave UART0 enabled or SD/eMMC will not work as PCI
@ -285,9 +287,6 @@ chip soc/intel/skylake
register "tcc_offset" = "3" # TCC of 97C
register "psys_pmax" = "101"
# PCH Trip Temperature in degree C
register "pch_trip_temp" = "75"
device cpu_cluster 0 on
device lapic 0 on end
end

5
src/mainboard/google/poppy/variants/nautilus/devicetree.cb
View File

@ -189,6 +189,7 @@ chip soc/intel/skylake
#| I2C3 | Pen |
#| I2C4 | Camera |
#| I2C5 | Audio |
#| pch_thermal_trip | PCH Trip Temperature |
#+-------------------+---------------------------+
register "common_soc_config" = "{
.chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT,
@ -247,6 +248,7 @@ chip soc/intel/skylake
.sda_hold = 36,
},
},
.pch_thermal_trip = 75,
}"
# Touch Screen
@ -291,9 +293,6 @@ chip soc/intel/skylake
# Use default SD card detect GPIO configuration
register "sdcard_cd_gpio_default" = "GPP_E15"
# PCH Trip Temperature in degree C
register "pch_trip_temp" = "75"
device cpu_cluster 0 on
device lapic 0 on end
end

3
src/mainboard/google/poppy/variants/nocturne/devicetree.cb
View File

@ -67,7 +67,6 @@ chip soc/intel/skylake
register "tdp_pl2_override" = "18"
register "psys_pmax" = "45"
register "tcc_offset" = "10"
register "pch_trip_temp" = "75"
register "pirqa_routing" = "PCH_IRQ11"
register "pirqb_routing" = "PCH_IRQ10"
@ -201,6 +200,7 @@ chip soc/intel/skylake
#| I2C3 | Camera |
#| I2C4 | Audio |
#| I2C5 | Rear Camera & SAR |
#| pch_thermal_trip | PCH Trip Temperature |
#+-------------------+---------------------------+
register "common_soc_config" = "{
.chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT,
@ -241,6 +241,7 @@ chip soc/intel/skylake
.speed_mhz = 1,
.early_init = 1,
},
.pch_thermal_trip = 75,
}"
# Touchscreen
register "i2c_voltage[0]" = "I2C_VOLTAGE_3V3"

5
src/mainboard/google/poppy/variants/rammus/devicetree.cb
View File

@ -172,6 +172,7 @@ chip soc/intel/skylake
#| I2C0 | Touchscreen |
#| I2C1 | Trackpad |
#| I2C5 | Audio |
#| pch_thermal_trip | PCH Trip Temperature |
#+-------------------+---------------------------+
register "common_soc_config" = "{
.chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT,
@ -207,6 +208,7 @@ chip soc/intel/skylake
.speed_mhz = 1,
.early_init = 1,
},
.pch_thermal_trip = 75,
}"
# Touchscreen
@ -242,9 +244,6 @@ chip soc/intel/skylake
# Use default SD card detect GPIO configuration
register "sdcard_cd_gpio_default" = "GPP_E15"
# PCH Trip Temperature in degree C
register "pch_trip_temp" = "75"
device cpu_cluster 0 on
device lapic 0 on end
end

5
src/mainboard/google/poppy/variants/soraka/devicetree.cb
View File

@ -179,6 +179,7 @@ chip soc/intel/skylake
#| I2C2 | Camera |
#| I2C4 | Camera |
#| I2C5 | Audio |
#| pch_thermal_trip | PCH Trip Temperature |
#+-------------------+---------------------------+
register "common_soc_config" = "{
.chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT,
@ -228,6 +229,7 @@ chip soc/intel/skylake
.sda_hold = 36,
},
},
.pch_thermal_trip = 75,
}"
# Touchscreen
@ -271,9 +273,6 @@ chip soc/intel/skylake
# Use default SD card detect GPIO configuration
register "sdcard_cd_gpio_default" = "GPP_E15"
# PCH Trip Temperature in degree C
register "pch_trip_temp" = "75"
device cpu_cluster 0 on
device lapic 0 on end
end

1
src/soc/intel/skylake/Kconfig
View File

@ -69,6 +69,7 @@ config CPU_SPECIFIC_OPTIONS
select SOC_INTEL_COMMON_BLOCK_SMM_IO_TRAP
select SOC_INTEL_COMMON_BLOCK_UART
select SOC_INTEL_COMMON_BLOCK_XHCI_ELOG
select SOC_INTEL_COMMON_BLOCK_THERMAL
select SOC_INTEL_COMMON_PCH_BASE
select SOC_INTEL_COMMON_NHLT
select SOC_INTEL_COMMON_RESET

1
src/soc/intel/skylake/Makefile.inc
View File

@ -64,7 +64,6 @@ ramstage-y += sd.c
ramstage-y += smmrelocate.c
ramstage-y += spi.c
ramstage-y += systemagent.c
ramstage-y += thermal.c
ramstage-y += uart.c
ramstage-y += vr_config.c
ramstage-y += xhci.c

3
src/soc/intel/skylake/chip.h
View File

@ -585,9 +585,6 @@ struct soc_intel_skylake_config {
*/
u8 IslVrCmd;
/* PCH Trip Temperature */
u8 pch_trip_temp;
/* Enable/Disable Sata power optimization */
u8 SataPwrOptEnable;
};

2
src/soc/intel/skylake/finalize.c
View File

@ -26,6 +26,7 @@
#include <intelblocks/lpc_lib.h>
#include <intelblocks/p2sb.h>
#include <intelblocks/pcr.h>
#include <intelblocks/thermal.h>
#include <reg_script.h>
#include <spi-generic.h>
#include <soc/me.h>
@ -35,7 +36,6 @@
#include <soc/pm.h>
#include <soc/smbus.h>
#include <soc/systemagent.h>
#include <soc/thermal.h>
#include <stdlib.h>
#include <timer.h>

24
src/soc/intel/skylake/include/soc/thermal.h
View File

@ -1,24 +0,0 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2017 Intel Corp.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#ifndef _SOC_THERMAL_H_
#define _SOC_THERMAL_H_
#define THERMAL_SENSOR_POWER_MANAGEMENT 0x1c
/* Enable thermal sensor power management */
void pch_thermal_configuration(void);
#endif

106
src/soc/intel/skylake/thermal.c
View File

@ -1,106 +0,0 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2017 Intel Corp.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <device/mmio.h>
#include <device/pci_ops.h>
#include <console/console.h>
#include <device/device.h>
#include <device/pci.h>
#include <soc/iomap.h>
#include <soc/pci_devs.h>
#include <soc/thermal.h>
#include "chip.h"
#define MAX_TRIP_TEMP 205
#define DEFAULT_TRIP_TEMP 50
static void *pch_thermal_get_bar(struct device *dev)
{
uintptr_t bar;
bar = pci_read_config32(dev, PCI_BASE_ADDRESS_0);
/*
* Bits [31:12] are the base address as per EDS for Thermal Device,
* Don't care about [11:0] bits
*/
return (void *)(bar & ~PCI_BASE_ADDRESS_MEM_ATTR_MASK);
}
static void pch_thermal_set_bar(struct device *dev, uintptr_t tempbar)
{
uint8_t pcireg;
/* Assign Resources to Thermal Device */
/* Clear BIT 1-2 of Command Register */
pcireg = pci_read_config8(dev, PCI_COMMAND);
pcireg &= ~(PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY);
pci_write_config8(dev, PCI_COMMAND, pcireg);
/* Program Temporary BAR for Thermal Device */
pci_write_config32(dev, PCI_BASE_ADDRESS_0, tempbar);
pci_write_config32(dev, PCI_BASE_ADDRESS_1, 0x0);
/* Enable Bus Master and MMIO Space */
pcireg = pci_read_config8(dev, PCI_COMMAND);
pcireg |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY;
pci_write_config8(dev, PCI_COMMAND, pcireg);
}
/* PCH Low Temp Threshold (LTT) */
static uint16_t pch_get_ltt_value(struct device *dev)
{
struct soc_intel_skylake_config *config;
uint16_t ltt_value;
uint16_t trip_temp = DEFAULT_TRIP_TEMP;
config = config_of(dev);
if (config->pch_trip_temp)
trip_temp = config->pch_trip_temp;
if (trip_temp > MAX_TRIP_TEMP)
die("Input PCH temp trip is higher than allowed range!");
/* Trip Point Temp = (LTT / 2 - 50 degree C) */
ltt_value = (trip_temp + 50) * 2;
return ltt_value;
}
/* Enable thermal sensor power management */
void pch_thermal_configuration(void)
{
uint16_t reg16;
struct device *dev = PCH_DEV_THERMAL;
if (!dev) {
printk(BIOS_ERR, "PCH_DEV_THERMAL device not found!\n");
return;
}
void *thermalbar = pch_thermal_get_bar(dev);
/* Use default pre-ram bar */
if (!thermalbar) {
pch_thermal_set_bar(dev, THERMAL_BASE_ADDRESS);
thermalbar = (void *)THERMAL_BASE_ADDRESS;
}
/* Set Low Temp Threshold (LTT) at TSPM offset 0x1c[8:0] */
reg16 = read16(thermalbar + THERMAL_SENSOR_POWER_MANAGEMENT);
reg16 &= ~0x1ff;
/* Low Temp Threshold (LTT) */
reg16 |= pch_get_ltt_value(dev);
write16(thermalbar + THERMAL_SENSOR_POWER_MANAGEMENT, reg16);
}