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intel/skylake: Force full memory train if RMT is enabled 

RMT is useless if the memory does not do a full training pass,
and since FSP does not seem to handle that case itself have
coreboot not pass in a valid set of saved training data so FSP
will do a full memory train.

BUG=chrome-os-partner:40635
BRANCH=none
TEST=build and boot twice on glados with p2 and RMT enabled
and see it do a full memory train on each boot.

Change-Id: Ia4f29a937e726a5a676f056ce8970086988da5b6
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Original-Commit-Id: f01e99204409899d4adbaebbe221b0348975cfa6
Original-Change-Id: I0bb193c5f3c9206a67315906745aad96a95b3f74
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/294067
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/11414
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This commit is contained in:
Duncan Laurie 2015-08-17 18:10:54 -07:00 committed by Patrick Georgi
parent 9dcd4f059b
commit c07cdfee08
1 changed files with 6 additions and 1 deletions
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7
src/soc/intel/skylake/romstage/romstage.c
View File

@ -103,7 +103,12 @@ void soc_memory_init_params(struct romstage_params *params,
upd->SataMode = config->SataMode;
upd->EnableTraceHub = config->EnableTraceHub;
upd->SaGv = config->SaGv;
upd->RMT = config->Rmt;
if (config->Rmt) {
upd->RMT = 1;
/* Force a full memory train if RMT is enabled */
params->pei_data->disable_saved_data = 1;
}
}
void soc_display_memory_init_params(const MEMORY_INIT_UPD *old,