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soc/intel/alderlake: Correct TCSS XHCI Port status offset 

The patch corrects TCSS XHCI Port status offset and CPU USB2 port count.
The information is captured from the ADL-P Processor EDS Volume 2b of 2
(DOC ID:619503).

BUG=None
TEST=Verified boot on Brya

Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Change-Id: I20c77d78f52277a9a979e11303cdb6cdabae7c59
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55230
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
This commit is contained in:
Sridhar Siricilla 2021-06-05 19:58:58 +05:30 committed by Tim Wawrzynczak
parent c54968d977
commit c07d2e5a9b
1 changed files with 2 additions and 2 deletions
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4
src/soc/intel/alderlake/xhci.c
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@ -15,8 +15,8 @@
#define PCH_XHCI_USB3_PORT_NUM 4
#define TCSS_XHCI_USB2_PORT_STATUS_REG 0x480
#define TCSS_XHCI_USB3_PORT_STATUS_REG 0x540
#define TCSS_XHCI_USB2_PORT_NUM 10
#define TCSS_XHCI_USB3_PORT_STATUS_REG 0x490
#define TCSS_XHCI_USB2_PORT_NUM 0
#define TCSS_XHCI_USB3_PORT_NUM 4
static const struct xhci_usb_info usb_info = {