Pit: move parade writes to mainboard.c
What gets written into the parade is highly mainboard-dependent. So the parade_writes array needs to be there. Change-Id: Ia382d9bf1929e67b7c14d7a09f5461b71866a16b Signed-off-by: Ronald G. Minnich <rminnich@google.com> Reviewed-on: https://gerrit.chromium.org/gerrit/61486 Reviewed-by: David Hendricks <dhendrix@chromium.org> Commit-Queue: Ronald G. Minnich <rminnich@chromium.org> Tested-by: Ronald G. Minnich <rminnich@chromium.org> Reviewed-on: http://review.coreboot.org/4362 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
This commit is contained in:
Ronald G. Minnich
Patrick Georgi
parent
3f17915361
commit
c0872f26d7
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@ -17,143 +17,19 @@
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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#include "ps8625.h"
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#include <device/i2c.h>
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#include <stdint.h>
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#include <stdlib.h>
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struct parade_write {
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uint8_t offset;
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uint8_t reg;
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uint8_t val;
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};
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#include "ps8625.h"
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static const struct parade_write parade_writes[] = {
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{ 0x02, 0xa1, 0x01 }, /* HPD low */
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/*
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* SW setting
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* [1:0] SW output 1.2V voltage is lower to 96%
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*/
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{ 0x04, 0x14, 0x01 },
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/*
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* RCO SS setting
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* [5:4] = b01 0.5%, b10 1%, b11 1.5%
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*/
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{ 0x04, 0xe3, 0x20 },
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{ 0x04, 0xe2, 0x80 }, /* [7] RCO SS enable */
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/*
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* RPHY Setting
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* [3:2] CDR tune wait cycle before
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* measure for fine tune b00: 1us,
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* 01: 0.5us, 10:2us, 11:4us.
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*/
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{ 0x04, 0x8a, 0x0c },
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{ 0x04, 0x89, 0x08 }, /* [3] RFD always on */
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/*
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* CTN lock in/out:
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* 20000ppm/80000ppm. Lock out 2
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* times.
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*/
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{ 0x04, 0x71, 0x2d },
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/*
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* 2.7G CDR settings
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* NOF=40LSB for HBR CDR setting
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*/
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{ 0x04, 0x7d, 0x07 },
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{ 0x04, 0x7b, 0x00 }, /* [1:0] Fmin=+4bands */
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{ 0x04, 0x7a, 0xfd }, /* [7:5] DCO_FTRNG=+-40% */
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/*
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* 1.62G CDR settings
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* [5:2]NOF=64LSB [1:0]DCO scale is 2/5
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*/
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{ 0x04, 0xc0, 0x12 },
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{ 0x04, 0xc1, 0x92 }, /* Gitune=-37% */
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{ 0x04, 0xc2, 0x1c }, /* Fbstep=100% */
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{ 0x04, 0x32, 0x80 }, /* [7] LOS signal disable */
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/*
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* RPIO Setting
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* [7:4] LVDS driver bias current :
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* 75% (250mV swing)
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*/
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{ 0x04, 0x00, 0xb0 },
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/*
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* [7:6] Right-bar GPIO output strength is 8mA
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*/
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{ 0x04, 0x15, 0x40 },
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/* EQ Training State Machine Setting */
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{ 0x04, 0x54, 0x10 }, /* RCO calibration start */
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/* [4:0] MAX_LANE_COUNT set to one lane */
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{ 0x01, 0x02, 0x81 },
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/* [4:0] LANE_COUNT_SET set to one lane */
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{ 0x01, 0x21, 0x81 },
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{ 0x00, 0x52, 0x20 },
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{ 0x00, 0xf1, 0x03 }, /* HPD CP toggle enable */
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{ 0x00, 0x62, 0x41 },
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/* Counter number, add 1ms counter delay */
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{ 0x00, 0xf6, 0x01 },
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/*
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* [6]PWM function control by
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* DPCD0040f[7], default is PWM
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* block always works.
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*/
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{ 0x00, 0x77, 0x06 },
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/*
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* 04h Adjust VTotal tolerance to
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* fix the 30Hz no display issue
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*/
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{ 0x00, 0x4c, 0x04 },
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/* DPCD00400='h00, Parade OUI = 'h001cf8 */
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{ 0x01, 0xc0, 0x00 },
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{ 0x01, 0xc1, 0x1c }, /* DPCD00401='h1c */
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{ 0x01, 0xc2, 0xf8 }, /* DPCD00402='hf8 */
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/*
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* DPCD403~408 = ASCII code
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* D2SLV5='h4432534c5635
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*/
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{ 0x01, 0xc3, 0x44 },
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{ 0x01, 0xc4, 0x32 }, /* DPCD404 */
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{ 0x01, 0xc5, 0x53 }, /* DPCD405 */
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{ 0x01, 0xc6, 0x4c }, /* DPCD406 */
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{ 0x01, 0xc7, 0x56 }, /* DPCD407 */
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{ 0x01, 0xc8, 0x35 }, /* DPCD408 */
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/*
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* DPCD40A, Initial Code major revision
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* '01'
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*/
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{ 0x01, 0xca, 0x01 },
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/* DPCD40B, Initial Code minor revision '05' */
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{ 0x01, 0xcb, 0x05 },
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/* DPCD720, Select internal PWM */
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{ 0x01, 0xa5, 0xa0 },
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/*
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* FFh for 100% PWM of brightness, 0h for 0%
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* brightness
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*/
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{ 0x01, 0xa7, 0xff },
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/*
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* Set LVDS output as 6bit-VESA mapping,
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* single LVDS channel
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*/
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{ 0x01, 0xcc, 0x13 },
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/* Enable SSC set by register */
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{ 0x02, 0xb1, 0x20 },
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/*
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* Set SSC enabled and +/-1% central
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* spreading
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*/
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{ 0x04, 0x10, 0x16 },
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/* MPU Clock source: LC => RCO */
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{ 0x04, 0x59, 0x60 },
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{ 0x04, 0x54, 0x14 }, /* LC -> RCO */
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{ 0x02, 0xa1, 0x91 } /* HPD high */
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};
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void parade_ps8625_bridge_setup(unsigned bus, unsigned chip_base)
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void parade_ps8625_bridge_setup(unsigned bus, unsigned chip_base,
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const struct parade_write *parade_writes,
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int parade_write_count)
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{
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int i;
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for (i = 0; i < ARRAY_SIZE(parade_writes); i++) {
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for (i = 0; i < parade_write_count; i++) {
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const struct parade_write *w = ¶de_writes[i];
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i2c_write(bus, chip_base + w->offset, w->reg, sizeof(w->reg),
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&w->val, sizeof(w->val));
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@ -20,6 +20,14 @@
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#ifndef __PS8625_H__
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#define __PS8625_H__
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void parade_ps8625_bridge_setup(unsigned bus, unsigned chip_base);
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struct parade_write {
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uint8_t offset;
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uint8_t reg;
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uint8_t val;
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};
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void parade_ps8625_bridge_setup(unsigned bus, unsigned chip_base,
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const struct parade_write *,
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int parade_write_count);
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#endif
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@ -51,6 +51,126 @@ static struct edid edid = {
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.bpp = 16,
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};
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static const struct parade_write parade_writes[] = {
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{ 0x02, 0xa1, 0x01 }, /* HPD low */
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/*
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* SW setting
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* [1:0] SW output 1.2V voltage is lower to 96%
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*/
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{ 0x04, 0x14, 0x01 },
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/*
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* RCO SS setting
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* [5:4] = b01 0.5%, b10 1%, b11 1.5%
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*/
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{ 0x04, 0xe3, 0x20 },
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{ 0x04, 0xe2, 0x80 }, /* [7] RCO SS enable */
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/*
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* RPHY Setting
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* [3:2] CDR tune wait cycle before
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* measure for fine tune b00: 1us,
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* 01: 0.5us, 10:2us, 11:4us.
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*/
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{ 0x04, 0x8a, 0x0c },
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{ 0x04, 0x89, 0x08 }, /* [3] RFD always on */
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/*
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* CTN lock in/out:
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* 20000ppm/80000ppm. Lock out 2
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* times.
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*/
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{ 0x04, 0x71, 0x2d },
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/*
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* 2.7G CDR settings
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* NOF=40LSB for HBR CDR setting
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*/
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{ 0x04, 0x7d, 0x07 },
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{ 0x04, 0x7b, 0x00 }, /* [1:0] Fmin=+4bands */
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{ 0x04, 0x7a, 0xfd }, /* [7:5] DCO_FTRNG=+-40% */
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/*
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* 1.62G CDR settings
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* [5:2]NOF=64LSB [1:0]DCO scale is 2/5
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*/
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{ 0x04, 0xc0, 0x12 },
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{ 0x04, 0xc1, 0x92 }, /* Gitune=-37% */
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{ 0x04, 0xc2, 0x1c }, /* Fbstep=100% */
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{ 0x04, 0x32, 0x80 }, /* [7] LOS signal disable */
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/*
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* RPIO Setting
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* [7:4] LVDS driver bias current :
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* 75% (250mV swing)
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*/
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{ 0x04, 0x00, 0xb0 },
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/*
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* [7:6] Right-bar GPIO output strength is 8mA
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*/
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{ 0x04, 0x15, 0x40 },
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/* EQ Training State Machine Setting */
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{ 0x04, 0x54, 0x10 }, /* RCO calibration start */
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/* [4:0] MAX_LANE_COUNT set to one lane */
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{ 0x01, 0x02, 0x81 },
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/* [4:0] LANE_COUNT_SET set to one lane */
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{ 0x01, 0x21, 0x81 },
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{ 0x00, 0x52, 0x20 },
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{ 0x00, 0xf1, 0x03 }, /* HPD CP toggle enable */
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{ 0x00, 0x62, 0x41 },
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/* Counter number, add 1ms counter delay */
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{ 0x00, 0xf6, 0x01 },
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/*
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* [6]PWM function control by
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* DPCD0040f[7], default is PWM
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* block always works.
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*/
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{ 0x00, 0x77, 0x06 },
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/*
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* 04h Adjust VTotal tolerance to
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* fix the 30Hz no display issue
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*/
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{ 0x00, 0x4c, 0x04 },
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/* DPCD00400='h00, Parade OUI = 'h001cf8 */
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{ 0x01, 0xc0, 0x00 },
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{ 0x01, 0xc1, 0x1c }, /* DPCD00401='h1c */
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{ 0x01, 0xc2, 0xf8 }, /* DPCD00402='hf8 */
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/*
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* DPCD403~408 = ASCII code
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* D2SLV5='h4432534c5635
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*/
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{ 0x01, 0xc3, 0x44 },
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{ 0x01, 0xc4, 0x32 }, /* DPCD404 */
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{ 0x01, 0xc5, 0x53 }, /* DPCD405 */
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{ 0x01, 0xc6, 0x4c }, /* DPCD406 */
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{ 0x01, 0xc7, 0x56 }, /* DPCD407 */
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{ 0x01, 0xc8, 0x35 }, /* DPCD408 */
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/*
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* DPCD40A, Initial Code major revision
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* '01'
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*/
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{ 0x01, 0xca, 0x01 },
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/* DPCD40B, Initial Code minor revision '05' */
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{ 0x01, 0xcb, 0x05 },
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/* DPCD720, Select internal PWM */
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{ 0x01, 0xa5, 0xa0 },
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/*
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* FFh for 100% PWM of brightness, 0h for 0%
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* brightness
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*/
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{ 0x01, 0xa7, 0xff },
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/*
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* Set LVDS output as 6bit-VESA mapping,
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* single LVDS channel
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*/
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{ 0x01, 0xcc, 0x13 },
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/* Enable SSC set by register */
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{ 0x02, 0xb1, 0x20 },
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/*
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* Set SSC enabled and +/-1% central
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* spreading
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*/
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{ 0x04, 0x10, 0x16 },
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/* MPU Clock source: LC => RCO */
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{ 0x04, 0x59, 0x60 },
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{ 0x04, 0x54, 0x14 }, /* LC -> RCO */
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{ 0x02, 0xa1, 0x91 } /* HPD high */
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};
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/* TODO: transplanted DP stuff, clean up once we have something that works */
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static enum exynos5_gpio_pin dp_pd_l = GPIO_X35; /* active low */
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static enum exynos5_gpio_pin dp_rst_l = GPIO_Y77; /* active low */
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@ -83,7 +203,9 @@ static void parade_dp_bridge_setup(void)
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exynos_pinmux_i2c7();
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i2c_init(7, 100000, 0x00);
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parade_ps8625_bridge_setup(7, 0x48);
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parade_ps8625_bridge_setup(7, 0x48,
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parade_writes,
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ARRAY_SIZE(parade_writes));
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}
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/*
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