binaryPI: Fix failing AP startup

Fix regression with commit 5639736

  binaryPI: Drop CAR teardown without POSTCAR_STAGE

Occassionally (maybe 1 boot in 10) SMP lapic_cpu_init() fails
with following errors in the logs of pcengines/apu2:

  CPU 0x03 would not start!
  CPU 0x03 did not initialize!

The CPU number is sometimes 0x02, never seen 0x01. Work-around also
suggests something to do with cache coherency and MTRRs that is really
at fault.

As a work-around return the BSP CAR teardown to use wbinvd instead
of invd. These platforms do not support S3 resume so this is the
easy work-around for the time being.

Change-Id: I3dac8785aaf4af5c7c105ec9dd0b95156b7cca21
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37438
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>

src/vendorcode/amd/pi/00630F01/binaryPI/gcccar.inc

@@ -904,7 +904,8 @@ fam15_disable_stack_remote_read_exit:
     btr     $INVD_WBINVD, %eax            # Disable INVD -> WBINVD conversion
     _WRMSR
 
-    invd
+    # An invd here sometimes breaks AP CPU startup ?
+    wbinvd
 
     #.if (bh == 01h) || (bh == 03h)      ; Is this TN or KV?
     cmp   $01, %bh

src/vendorcode/amd/pi/00660F01/binaryPI/gcccar.inc

@@ -639,7 +639,8 @@ fam15_disable_stack_remote_read_exit:
     btr     $INVD_WBINVD, %eax            # Disable INVD -> WBINVD conversion
     _WRMSR
 
-    invd
+    # An invd here sometimes breaks AP CPU startup ?
+    wbinvd
 
 #    #.if (bh == 01h) || (bh == 03h)      ; Is this TN or KM?
 #    cmp   $01, %bh

src/vendorcode/amd/pi/00730F01/binaryPI/gcccar.inc

@@ -603,7 +603,8 @@ fam16_disable_stack_remote_read_exit:
     btr     $INVD_WBINVD, %eax            # Disable INVD -> WBINVD conversion
     _WRMSR
 
-    invd
+    # An invd here sometimes breaks AP CPU startup
+    wbinvd
 
     #Do Standard Family 16 work
     mov     $HWCR, %ecx                    # MSR:C001_0015h