soc/amd/common/block: move binaryPI S3 block into PI block

The code in soc/amd/common/block/s3 is specific to the AMD binaryPI
coreboot integration, so move the code to soc/amd/common/block/pi. This
drops the SOC_AMD_COMMON_BLOCK_S3 Kconfig option and integrates the
dependencies and selections into the SOC_AMD_COMMON_BLOCK_PI Kconfig
option. Since only selecting SOC_AMD_COMMON_BLOCK_PI but not
SOC_AMD_COMMON_BLOCK_S3 resulted in missing functions in the linking
process, we don't lose support for any working configuration by only
having one Kconfig option for both parts.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ib2bd99a88d8b05216688bc45d9c4f23a007ce870
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57883
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>

src/soc/amd/common/block/pi/Kconfig

@@ -1,9 +1,12 @@
 config SOC_AMD_COMMON_BLOCK_PI
 	bool
+	depends on SOC_AMD_COMMON_BLOCK_ACPI
+	select CACHE_MRC_SETTINGS
 	select HAVE_DEBUG_RAM_SETUP
+	select MRC_WRITE_NV_LATE
 	help
 	  This option builds functions that interface AMD's AGESA reference
-	  code packaged in the binaryPI form.
+	  code packaged in the binaryPI form and S3-related functionality.
 
 if SOC_AMD_COMMON_BLOCK_PI
 

src/soc/amd/common/block/pi/Makefile.inc

@@ -5,6 +5,7 @@ romstage-y += def_callouts.c
 romstage-y += heapmanager.c
 romstage-y += image.c
 romstage-y += refcode_loader.c
+romstage-y += s3_resume.c
 
 ramstage-y += agesawrapper.c
 ramstage-y += amd_late_init.c
@@ -13,5 +14,6 @@ ramstage-y += def_callouts.c
 ramstage-y += heapmanager.c
 ramstage-y += image.c
 ramstage-y += refcode_loader.c
+ramstage-y += s3_resume.c
 
 endif # CONFIG_SOC_AMD_COMMON_BLOCK_PI

src/soc/amd/common/block/s3/Kconfig

@@ -1,7 +0,0 @@
-config SOC_AMD_COMMON_BLOCK_S3
-	bool
-	depends on SOC_AMD_COMMON_BLOCK_ACPI
-	select CACHE_MRC_SETTINGS
-	select MRC_WRITE_NV_LATE
-	help
-	  Select this option to add S3 related functions to the build.

src/soc/amd/common/block/s3/Makefile.inc

@@ -1,6 +0,0 @@
-ifeq ($(CONFIG_SOC_AMD_COMMON_BLOCK_S3),y)
-
-romstage-y += s3_resume.c
-ramstage-y += s3_resume.c
-
-endif # CONFIG_SOC_AMD_COMMON_BLOCK_S3

src/soc/amd/stoneyridge/Kconfig

@@ -39,7 +39,6 @@ config CPU_SPECIFIC_OPTIONS
 	select SOC_AMD_COMMON_BLOCK_PI
 	select SOC_AMD_COMMON_BLOCK_PM
 	select SOC_AMD_COMMON_BLOCK_PSP_GEN1
-	select SOC_AMD_COMMON_BLOCK_S3
 	select SOC_AMD_COMMON_BLOCK_SATA
 	select SOC_AMD_COMMON_BLOCK_SMBUS
 	select SOC_AMD_COMMON_BLOCK_SMI